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10 articles for “digital signal processor (DSP)”
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGAS
Abstract: Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 3, 2021 · pp. 29–34 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Implementation of an Adaptive Filter Algorithm with Subband Filtering Approach on Acoustic Echo Cancellation
Abstract: This paper focuses on model and its realization on digital signal processors (DSP) for suppressing annoying acoustic echoes in telephone and mobile communication applications. For cost sensitive subscriber devices and high quality voice communications the aims are 1) minimum computational complexity 2) maximum convergence speed and 3) maximum echo attenuation. The chosen method for the echo cancellation involves a sub band decomposition performing the adaptive filtering in subbands at a …
Published in Current Trends in Signal Processing · Vol. 4, Issue 3, 2014 · pp. 28–34 Read article
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Implementation of 16-Bit Qam Using Texas Instruments
Abstract: In this paper, an implementation of 16-bit QAM is performed where there is a high use of Digital Video Broadcasting Cable (DVB-C), as there is increase in the usage the bandwidth requirement for each user is mutually increasing. Due to this, there is spectral congestion caused and drastic improvements have been taken in the field of communications. QAM multilevel modulation can offer an attractive solution to current bandwidth restriction in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 2, 2015 · pp. 14–20 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Comparative Analysis of Partial Product Addition in Vedic Urdhva Tiryakbhyam Multiplier
Abstract: Multiplication is one of important operations performed in many digital signal processing applications. Hence the performance of the multiplier will affect the overall performance of the DSP processor. The methods like booth multiplier, and array multiplier are used. Vedic multiplication technique had proved its importance in getting the speed of multiplication. It is required to add the generated partial products quickly, to generate the result of multiplication faster. To add …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 15–32 Read article
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Graphene–Perovskite Hybrid Opto-Electronic Modulators for Ultra-Low Power Optical Communication
Abstract: This paper proposes a novel self-adaptive neuromorphic opto-electronic transceiver architecture designed to enhance the intelligence, adaptability, and efficiency of next-generation optical communication networks. The proposed system integrates neuromorphic computing principles with photonic signal processing to enable real-time learning, dynamic resource allocation, and autonomous compensation of channel impairments such as dispersion, nonlinearities, and noise. Unlike conventional transceivers, the developed model employs spiking neural networks embedded within opto-electronic circuits to mimic biological …
Published in Trends in Opto-electro & Optical Communication · Vol. 16, Issue 1, 2026 · pp. 41–52 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article