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12 articles for “Static Noise Margins”
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A Reliable Low Standby Power 6T SRAM Cell
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 33–59 Read article
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Stability Analysis in SRAM Cell for Deep Submicron Design
Abstract: AbstractMemory is an integral part of present day battery operated and hand held electronic gadgets. As the size of devices shrinks so does the size of memory used in these devices also, this increases the demand for low power devices. Leakage current is one of the prominent factors that contribute to significant portion of the total power dissipation; in fact at lower technologies it becomes comparable to switching component. Device …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 2, 2018 · pp. 1–6 Read article
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Design and Implementation of Low Power and High Speed 10T SRAM with High SNM
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell utilizes a strong cross-coupled structure that combines a standard inverter with a stacked transistor and a Schmitt-trigger inverter with a double-length pull-up transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 40–65 Read article
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Characterization of a Single-Ended Schmitt-Trigger based 9T SRAM Cell
Abstract: Data stability is a prime concern in submicron regime. This work presents a single-ended Schmitt- trigger (ST) based 9T static random-access memory (SRAM) cell. Proposed design provides enhanced read stability as it uses ST based inverters. Low power dissipation is achieved by employing just a single bit line. Simulation is carried out on gpdk 180nm CMOS technology on Cadence. Proposed design offers 1.36x improvement in read static noise margin (RSNM) …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 26–31 Read article
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Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability
Abstract: In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memory (SRAM) cell. The proposed cell employs cross-point data aware write structure, and thus supports bit interleaving architecture to mitigate soft errors. The proposed cell does not suffer from read disturbance as bit line is completely isolated from bit storage node. Simulation is done on 180 nm CMOS technology on Cadence. Read static noise margin (RSNM) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 5–10 Read article
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A Double-Ended Read-Decoupled 8T SRAM Cell with Improved Read Stability and Access Time at 45 nm Technology
Abstract: AbstractDue to rampant leveling of instrument measurements, the stability of an SRAM cell is the biggest anxiety for upcoming technology. In this paper, it is introduced by an 8T (8-transistor) SRAM cell. The enlarged data stability is offered by proposed cell until read operation. The voltage scale of the node keeping ‘0’ is enlarged by introduced cell and thus it achieves a near butterfly curve that is vital to creation …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 2, 2017 · pp. 29–33 Read article
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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell
Abstract: VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 73–77 Read article
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Designing and Testing of various types of SRAM topologies with 90nm Technology
Abstract: VLSI technology provides a way for designing compact devices which are useful to human for leading their day to day, the advancement in the technology provides high speed and power consuming appliances. In this category, intend to design an application with high data rate and low power, memory efficient device and Static Random-Access Memory (SRAM) is structured. Improvement in the technology comprises of scaling down the design process and impact …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 12–16 Read article
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Performance and Analysis of 6T, 8T & 10T SRAM Cell in 28nm Technology
Abstract: Technology scaling into deep sub-micron regimes has significantly increased the design challenges of Static Random Access Memory (SRAM), particularly at the 28 nm technology node. As transistor dimensions shrink, SRAM cells become more vulnerable to stability degradation, leakage current, process variations, and reduced noise margins, which adversely affect overall memory performance and reliability. The conventional 6T SRAM cell remains widely used due to its compact structure and high storage density; …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article
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Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell
Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article
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Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article