Search
36 articles for “Network-on-Chip”
-
Design of Core Based System-On-Chip Using Interfaced Cores and Routers in Network-On-Chip
Abstract: AbstractNetwork-On-Chip (NOC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. NOC has emerged as a new paradigm for designing core based System-on-Chip (SOC). Network-on-Chip is seen as a scalable solution facilitating the development of system-on-chip with an increasing number of IP cores. The idea of using on chip packet switched networks for interconnecting a large …
Published in Journal of Mobile Computing, Communications & Mobile Networks · Vol. 4, Issue 3, 2017 · pp. 17–24 Read article
-
Low Power and Area Efficient System Achieved by using Efficient Virtual Channels on Network on Chip
Abstract: In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in a router are included. However, if the router includes five I/O ports, then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, smart power-saving (SPS), for low power consumption and low area in virtual channels …
Published in Journal Of Network security · Vol. 4, Issue 2, 2016 · pp. 36–41 Read article
-
A Reliable Routing Architecture and Algorithm for Network-on-Chip
Abstract: The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 40–48 Read article
-
Design of a 4X4 Network-on-Chip Crossbar Router in a System-on-Chip
Abstract: With the number of IPs increasing in an SoC, there is a need for achieving high bandwidth, low latency, scalable multi-core intercommunication and solve the shortcoming of buses. Network-on-chip is a technology which is a solution for such problems. Network-on-chip solves the problem by implementing a communication network of switches, routers and resources. This paper proposes a design for communication among subsystems between intellectual property cores in an SoC design. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 3, 2015 · pp. 28–35 Read article
-
VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter
Abstract: As the technology progresses, a large number of devices can be incorporated into a single chip. So, the communication between these devices becomes critical. The network-on-chip (NoC) is a technology used for such communication and overcomes the constraints of traditional bus-based system-on-chip (SoC). Router is the backbone of NoC and determines the performance to a great extent. This paper focuses on the implementation of five port virtual channel router which …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 88–93 Read article
-
A Novel Approach Based On-Chip High Speed Optical Interconnection Network
Abstract: On-chip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication problem and obtain high-performance integrated circuits. On-chip interconnects are an important performance limiting factor in present day VLSI design. Performance optimization has always been a critical step in the designing of integrated circuits. In this paper, an optical interconnect in 1550 nm range is being implemented using opti-system software. A novel approach is …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 41–48 Read article
-
Mirror-Symmetric NoC Topologies for 64-Core Arrays: Investigating Latency and Energy Trade-offs versus Mesh and Torus Interconnects for Block-Level Matrix Multiplication Workloads
Abstract: Modern chip multiprocessors increasingly rely on many-core arrays to accelerate dense linear algebra kernels such as block-level general matrix multiplication (GEMM), where inter-tile communication often rivals computation cost. Network-on-Chip (NoC) topology therefore strongly influences overall latency and energy efficiency. This work proposes a mirror-symmetric NoC topology for 64-core arrays, in which long-range bypass links are added about a central reflective axis to shorten paths between symmetric core partitions that frequently …
Published in Journal of Operating Systems Development & Trends · Vol. 13, Issue 2, 2026 · pp. 35–44 Read article
-
Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article
-
A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network
Abstract: Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately, solve the communication problem, and to obtain high-performance integrated circuits. In this study, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to fulfill the requirements of silicon-based ICs must satisfy to successfully perform copper electrical interconnects (IEs). Keywords: Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonicsCite this ArticleAbhishek Sharma, Sudhir Kumar …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 36–44 Read article
-
Multimodal Generative AI for Vehicular Applications at Edge
Abstract: This paper explores how the rapid advancements in vehicular technology, including autonomous driving and intelligent transportation systems, have driven the need for real-time data processing and decision-making. Multimodal generative AI, when deployed at the edge, offers a powerful solution for vehicular applications by leveraging diverse data sources such as video, audio, sensor inputs, and environmental data. This paper explores the integration of multimodal generative AI with edge computing in vehicular …
Published in Journal of Control & Instrumentation · Vol. 16, Issue 1, 2025 · pp. 27–34 Read article
-
A Physics-Informed Graph Neural Network Framework for Real- Time Thermal-Aware Fault Prediction and Adaptive Power Optimization in Heterogeneous System-on-Chip Architectures
Abstract: Heterogeneous System-on-Chip (SoC) architectures are increasingly adopted in edge computing, artificial intelligence, autonomous systems, and high-performance embedded platforms due to their superior computational efficiency and flexibility. However, increasing integration density and workload diversity introduce severe thermal hotspots, accelerated device degradation, and unexpected hardware faults that adversely affect system reliability and energy efficiency. This study proposes a Physics-Informed Graph Neural Network (PI-GNN) framework for real-time thermal- aware fault prediction and adaptive …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 19–28 Read article
-
Investigative Study of Adaptive Fault Tolerance in Optical Networks
Abstract: Optical networks have become the backbone of modern telecommunications infrastructure, enabling high-speed data transmission across global networks. However, these networks face significant reliability challenges due to component failures, signal degradation, and environmental factors. This investigative study examines adaptive fault tolerance mechanisms in optical networks, focusing on emerging technologies and methodologies that enhance network resilience. The research analyzes various fault detection techniques, including machine learning-based approaches, self-healing protocols, and dynamic reconfiguration …
Published in Trends in Opto-electro & Optical Communication · Vol. 15, Issue 2, 2025 · pp. 24–30 Read article
-
New trends in Radio Frequency design and making things smaller
Abstract: Recent improvements in wireless communication, the Internet of Things (IoT), and 5G/6G networks have made people want small, powerful radio frequency (RF) equipment. With an emphasis on how developments in materials engineering, circuit architecture, and packaging technologies are redefining RF system integration, this article offers a thorough evaluation of current developments in RF downsizing. System-on-Chip (SoC), System-in-Package (SiP), and Antenna-in-Package (AiP) ideas, which allow tightly integrated RF front-ends with enhanced …
Published in International Journal of Radio Frequency Innovations · Vol. 3, Issue 2, 2025 · pp. 28–34 Read article
-
A Five-Layer Architectural Framework for Sustainable and Scalable AI Systems
Abstract: Artificial Intelligence (AI) is not only about algorithms. AI works like a full “stack” of layers, from electricity to real-world user applications. In this paper, we explain a simple and student-friendly Five- Layer Architecture of AI: (1) Energy, (2) Chips, (3) Infrastructure, (4) Models, and (5) Applications. Each layer supports the next layer, like a cake with multiple layers. If any layer is weak, AI systems become slow, costly, or …
Published in Journal of Artificial Intelligence Research & Advances · Vol. 13, Issue 3, 2025 Read article
-
Literature Survey of On-chip Architectures and Arbitration Algorithms
Abstract: Today micro-electronic products are influencing the ways of communication, learning and entertainment. The key driving force for the developments during decades is the System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips. Not only functionally enriched, these products such as mobile phones, notebooks and personal handheld sets are becoming faster, smaller-in-size, larger-in-capacity, lighter-in-weight, lower-in-power-consumption and cheaper. In this survey, communication architectures of SoC are discussed whose design …
Published in Journal of Microcontroller Engineering and Applications · Vol. 4, Issue 1, 2017 · pp. 17–23 Read article
-
Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
-
Unleashing the Power of Human Body for Communication with RedTacton
Abstract: "Red Tacton" refers to the most recent advanced technology utilized as a communication network within the human body. NTT, which stands for Nippon Telegraph and Telephone Corporation, developed the Human Area Network (HAN) in Japan. RedTacton is a technology that utilizes the low field created by the human body to transmit data effectively. This ground-breaking technology uses the surface of the human body to transmit data securely and quickly. The …
Published in Trends in Opto-electro & Optical Communication · Vol. 12, Issue 3, 2022 · pp. 19–23 Read article
-
Artificial Neural Network Implementation in FPGA using Multiplexer-based Weight Updating for Efficient Resource Utilization
Abstract: This paper presents a novel scheme for field-programmable gate array (FPGA) implementation of an artificial neural network (ANN). The proposed implementation is aimed at reducing resource requirement, without compromising on the speed so that a complex ANN architecture could be realized on a single chip at a lower cost. The weight updating process in different layers of the ANN has been carried using a simple MUX-based architecture. Backpropagation algorithm which …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 1–5 Read article
-
FACE EMOTION RECOGNITION TO DETECT DEPRESSION
Abstract: In the current competitive world, one of the most familiar and grave mental illness we encounter in humans is Depression also called as major depression or major depressive disorder. It makes you feel depressed and disinterested all the time, which has a bad impact on your thoughts and behaviour. Thus affecting not only the victim but also people associated with them, such as family, friends and society. If not treated …
Published in Current Trends in Signal Processing · Vol. 14, Issue 1, 2024 · pp. 1–14 Read article
-
Detection of Driver Emotion Using Deep Learning
Abstract: High level Driver-Help Frameworks (ADASs) are utilized for expanding security in the auto space, yet momentum ADASs quite work without considering drivers' states, e.g., whether she/he is genuinely able to drive. Feelings are a significant way of behaving of people and may emerge in driving circumstances. Uncontrolled feelings can prompt unsafe impacts. To control and decrease the adverse consequence of conduct. In this paper we will distinguish the driver’s conduct. …
Published in International Journal of Electronics Automation · Vol. 1, Issue 1, 2023 · pp. 01–06 Read article