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56 articles for “Multi Gate”
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Study and Analysis on Multi-gate MOSFET Design
Abstract: AbstractMulti-gate MOSFET is the emerging technology that is used in the area of low-power VLSI design. Multi-gate devices provide much better advantages over conventional MOSFET. As less power dissipation, decrease size, and more operational value could be obtained. Multi-gate MOSFET devices also reduce cost of production. Thus, design of electronics devices based on multi-gate technology is beneficial in today’s requirement. Basic MOSFET due to its reduction in size shows short …
Published in Journal of Semiconductor Devices and Circuits · Vol. 7, Issue 1, 2020 · pp. 1–7 Read article
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3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters
Abstract: Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper. Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 2, 2014 · pp. 1–8 Read article
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Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology
Abstract: AbstractThis paper presents the design and analysis of double gate FinFET complimentary pass transistor logic (CPL) multiplexer. The circuit of multiplexer (MUX) using CPL is used for comparison of performance parameters like average power consumption, rise/fall time, delay, slew rate, PDP and EDP. Multiplexer is a digital circuit, it has inputs and select line; select lines are used for select input lines to transfer data to the output end. The …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 41–48 Read article
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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Sub-nano Regime DG-MOSFETs
Abstract: AbstractThe significance of device performance of Gallium Nitride based double gate metal-oxide- semiconductor field-effect-transistor has been executed. The simulations were done by Silvaco Atlas simulation software with focusing on non-equilibrium green function (NEGF). Multiple gate length (LG=9.1 nm) was observed to distinguish the transfer characteristics curve. The other concentration was observed for device ON-State Current (ION), OFF-State Current (IOFF), Drain Induced Barrier Lowering (DIBL), Sub Threshold Slope (SS) and Electric …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 1–6 Read article
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Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic
Abstract: Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 21–28 Read article
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
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Performance Evaluation of Single Phase Cascaded Nine Level Inverter using Photovoltaic (PV) SystemPerformance Evaluation of Single Phase Cascaded Nine Level Inverter using Photovoltaic (PV) System
Abstract: Multilevel inverters are considered at present as the state of the art power conversion systems for high power and power quality demanding applications. This paper’s objective is to propose a modified cascaded nine-level inverter topology for a virtually sinusoidal output voltage, less number of power switches, results in decreased complexity and reduced total harmonic distortion (THD). The structure is simple and easy to be extended to higher level but also …
Published in Trends in Electrical Engineering · Vol. 8, Issue 1, 2018 · pp. 30–47 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Monitoring and Safety of Aircraft using Wireless Technology
Abstract: Traditional aircraft sensor networks, burdened by wire complexity and high-power demands, struggle with scalability and real-time data acquisition. This paper proposes Bluetooth Low Energy advertising as a transformative solution, leveraging its lightweight, energy-efficient, and secure nature within tree network architecture. Sensors broadcast data packets picked up by strategically placed gateways, enabling efficient data dissemination through multi-hop relaying. The approach boasts scalability due to minimal hardware and power requirements, leading to …
Published in International Journal of Satellite Remote Sensing · Vol. 1, Issue 2, 2023 · pp. 14–21 Read article
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Novel MOSFET Based Pressure Sensor That Uses Combined Channel Piezoresistance and Gate Capacitance Effects
Abstract: The paper considers modeling and analysis of a square and circular diaphragm Suspended Gate MOSFET based pressure sensor using COMSOL Multiphysics. Two structures, one a square with an n-channel MOSFET at the center and the second a circle with a p-channel MOSFET at the edge of the diaphragm were simulated. The piezoresistance effect of the channel and capacitance variation due to the suspended gate have been exploited in designing the …
Published in Recent Trends in Sensor Research & Technology · Vol. 2, Issue 2, 2015 · pp. 30–39 Read article
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Swing Restored Low Power and Area Efficient 8-bit Arithmetic Logic Unit Using Modified Gate Diffusion Input Technique
Abstract: AbstractThe arithmetic logic unit (ALU) is one of the most fundamental operational units in any processor. The ALU is the heart of any system or any processor and the core component of the central processing unit because mainly all the fundamental operations are performed by the help of ALU only. So, it can be defined as the combinational unit that is used to perform its logical and arithmetic units. The …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 19–29 Read article
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Low Power Area Efficient 4×4 Vedic Multiplier using GDI half adders with Better Delay Performance
Abstract: In the field of VLSI, wireless communication and digital signal processing, low power and area efficient architectures are considered. Majority of such applications uses multiplication. The multiplication is done using repetitive addition and shift and add method. It consumes more area delay and power. Vedic multiplier is one of the efficient multiplier. It is designed using different Vedic techniques or sutras, which reduces the area, power consumption and provide better …
Published in Journal of Control & Instrumentation · Vol. 10, Issue 2, 2019 · pp. 28–39 Read article
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Adaptive Neuro-Fuzzy Inference System (ANFIS) Control for Total Harmonic Distortions Reduction of Multi-Pulse STATCOM
Abstract: In this paper proposed ANFIS System is adapted for controllable mitigation of Total harmonic distortions of STATCOM with Multiple pulse technology. Integrated power electronics device, Gate Turn Off (GTO) is used in switching mode with Voltage source convertor during application of distinct load conditions. The proportional and integrated Controller is replaced by a smart fuzzy logic controller that offers great support for harmonic mitigation by redefining the electrical magnitudes of …
Published in Journal of Mechatronics and Automation · Vol. 9, Issue 2, 2022 · pp. 17–31` Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Artificial Neural Network Implementation in FPGA using Multiplexer-based Weight Updating for Efficient Resource Utilization
Abstract: This paper presents a novel scheme for field-programmable gate array (FPGA) implementation of an artificial neural network (ANN). The proposed implementation is aimed at reducing resource requirement, without compromising on the speed so that a complex ANN architecture could be realized on a single chip at a lower cost. The weight updating process in different layers of the ANN has been carried using a simple MUX-based architecture. Backpropagation algorithm which …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 1–5 Read article