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69 articles for “Gate voltage”
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Studies on the Variations of Drain Current in Gallium Nitride based High Electron Mobility Transistors
Abstract: AbstractIn this work, total 2477 individual simulation outputs are reported. Variations in drain current with respect to the electrical parameters (drain voltage and gate voltage) and structural parameters of high electron mobility transistors (HEMTs) have been studied. The drain current is higher corresponding to larger aluminium mole fraction. This study will be useful to fabricate the HEMT based biomedical sensors.Keywords: Drain current, drain voltage, gate voltage, high electron mobility transistorCite …
Published in Journal of Microwave Engineering and Technologies · Vol. 5, Issue 1, 2018 · pp. 13–24 Read article
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Studies on the Electrical Characteristics of AlGaAs/GaAs High Electron Mobility Transistors
Abstract: AbstractIn this work, total 5722 individual simulation outputs are reported. The effects of drain voltage, gate voltage, aluminium mole fraction, and gate length on drain current are studied in AlGaAs/GaAs high electron mobility transistors (HEMTs). The linear region and saturation region are prominent in each drain characteristic curve. The drain current reduces in the structure of larger gate length. This work is useful to fabricate the HEMT based biomedical sensors. …
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 5, Issue 3, 2018 · pp. 30–40 Read article
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Studies on the DC Characteristics of Nanoelectronic Single-Heterojunction GaN based HEMTs with AlGaN Layer of 22 nm
Abstract: AbstractIn this work, total 2367 individual simulation-outputs are reported. We have studied the drain characteristics in AlGaN/GaN high electron mobility transistors (HEMTs) having the AlGaN thickness of 22 nm. According to this study, the drain current increases with drain voltage. Also, the drain current increases with gate voltage. The drain current is observed as higher at larger aluminium mole fraction. Also, the drain current is higher at larger doping concentration. …
Published in Journal of Microwave Engineering and Technologies · Vol. 5, Issue 1, 2018 · pp. 1–12 Read article
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Report on the Novel Electrical Characteristics of Microelectronic High Electron Mobility Transistors to Establish a Low-Cost Microelectronics Laboratory in the National Institute of Technology Arunachal Pradesh
Abstract: AbstractIn this work, total 22584 individual simulation-outputs are reported according to the performed simulation-studies on the microelectronic AlGaN/GaN high electron mobility transistors (HEMTs). This series of simulation work has been performed using the SILVACO-ATLAS software tool on the basis of already established theories related to the semiconductor-physics of HEMTs. In this work, the drain characteristics are investigated with respect to the aluminium mole fraction, drain voltage, gate voltage, gate length …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 2, 2017 · pp. 6–28 Read article
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Simulation Studies on the Drain Characteristics of Microelectronic AlGaN/GaN HEMTs Corresponding to the 30 nm of AlGaN Nano-Layer
Abstract: AbstractIn this work, the simulation studies are performed on high electron mobility transistor (HEMT) structures using the SILVACO-ATLAS software tool. The drain characteristics of HEMT structures is investigated with respect to the Aluminium mole fraction, drain voltage, gate voltage, and gate length at 30 nm thickness of AlGaN nano-layer. The simulation studies on the effect of gate length to control the drain characteristics are a novelty of this work. The …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 1, 2017 · pp. 8–16 Read article
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Experimental Investigations to Improve the Electrical Characteristics of Nitride-Based Nanoelectronic High Electron Mobility Transistors
Abstract: In this work, the DC and RF performances of conventional nanoelectronic high electron mobility transistor (HEMT) are compared with those of two individually modified HEMT structures in a nano-scale regime. All simulation results are produced by the SILVACO- ATLAS physical simulator according to the performed designs of HEMT structures. In each of these HEMT structures, the formation of quantum well is demonstrated at unbiased condition. In the DC analysis of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 1, 2021 · pp. 14–30 Read article
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A Two-Dimensional (2D) Analytical Model for Channel Potential and Threshold Voltage of Short Channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET
Abstract: In the present paper, an analytical model for the channel potential of short channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET has been presented using parabolic approximation method. Further, the threshold voltage of the device has been calculated using minimum mid channel potential and the result obtained has been compared with the threshold voltage of Triple Material double gate (TMDG) MOSFET in order to show the improvement in the threshold …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 13–25 Read article
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Effect of Aluminium Nitride Layer on the Electrical Performance of Microelectronic HEMTs
Abstract: AbstractIn this simulation work, a series of simulation outputs are reported related to the AlGaN/GaN single-heterojunction high electron mobility transistors (HEMTs). The effect of aluminium nitride nucleation layer on the drain characteristics is significant in single-heterojunction AlGaN/GaN HEMTs. The effects of drain voltage and gate voltage on the drain current are studied in the designed and simulated device structures. This simulation work may be a useful prediction to fabricate the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 9–12 Read article
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Variations of Source Current in the Double-Heterojunction HEMTs
Abstract: AbstractIn this report, we have studied the variations in source current with respect to drain voltage corresponding to the double heterojunction (DH) high electron mobility transistors (HEMTs). Also, the effects of gate voltage and aluminium mole fractions on source current are studied. In this work, the highest source current achieved is 3.3 mA. This work may be useful to design many nanoelectronic HEMTs.Keywords: Source current, drain voltage, gate voltage, mole …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 3, 2016 · pp. 19–24 Read article
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Novel Characteristics of GaN based Nanoelectronic Double-Heterojunction HEMTs to Establish a Solid-State-Electronics Laboratory
Abstract: The drain characteristics are investigated with respect to electrical variables (drain voltage, gate voltage) and structural parameters of high electron mobility transistors (HEMTs). Total 10526 individual simulation-outputs are reported in this work. The maximum drain current of 553 mA is achieved by the simulated structures of double-heterojunction HEMTs using the SILVACO-ATLAS software tool. The drain current is higher at shorter gate length. The drain current is higher at larger aluminium …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 3, 2017 · pp. 11–20 Read article
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Simulation Studies on the Electrical Characteristics of Novel Nanoelectronic AlGaN/GaN/AlGaN Double-Heterojunction HEMTs for Industrial Applications
Abstract: AbstractWe report the drain characteristics of AlGaN/GaN/AlGaN double heterojunction (DH) high electron mobility transistors (HEMTs) with the associated quantum well depths. The drain current is higher corresponding to the larger doping concentration of AlGaN nano-layer. The drain current is higher with the larger gate voltage at any particular drain voltage. The quantum well depth is significantly higher with the increasing doping concentration of AlGaN nano-layer. About the novelty of this …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 3, 2016 · pp. 6–18 Read article
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Optimization and Analysis of InGaAs Vertical Nanowire Transistor for Memory Array Applications
Abstract: In this paper, we present a cylindrical gate all around In 0.53 Ga 0.47 As Vertical Nanowire Transistor (VNWT) on silicon at ultra-shortchannel gate length 14nm by numerical simulation approach. The In 0.53 Ga 0.47 As VNWT device dimensions like diameter, source and drainextension length and channel doping are taken as critical process parameters and optimized for better performance. The proposed device isscalable up-to 10nm with a maximum On-current of …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 32–44 Read article
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A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions
Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article
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Simulation Studies on the Electrical Characteristics of High Electron Mobility Transistors
Abstract: AbstractSimulation studies have been performed on the AlGaN/GaN high electron mobility transistor (HEMT) with AlN spacer layer. The current-voltage characteristics have been studied with respect to different gate voltages and different doping concentrations. Studies have been performed on the quantum well depth variation corresponding to the designed HEMTs.Keywords: Doping, drain current, drain voltage, quantum wellCite this ArticleSanjib Kalita, Ashish Prajapati, Susanta Sinha Roy, Jyoti Prasad Banerjee, James Andrew McLaughlin, Subhadeep …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 2, 2016 · pp. 32–36 Read article
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Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design
Abstract: Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 15–20 Read article
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Design and Analysis of Inverters using Double Gate MOSFET
Abstract: AbstractThe double gate MOSFET is a form of MOSFET where two gates are fabricated along the length of the channel, one after another. There are several applications of double gate MOSFETs. It is possible to design logic gates using double gate MOSFETs. It is one of the digital applications of it. This paper interprets the design and analysis of different types of inverters using DG-MOSFET. The advantages of using DG-MOSFET …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 1, 2017 · pp. 1–7 Read article
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Investigation of the Hall and Nernst-Ettingshausen Effects in Diluted Magnetic Semiconductors
Abstract: This review explores the Hall and Nernst-Ettingshausen effects in various magnetic systems, including diluted magnetic semiconductors (DMS), topological insulators, superconductors, and novel composite materials. In DMS, the interplay of ferromagnetism and magnetic impurities introduces unique transport behaviors, particularly influencing the anomalous Hall effect (AHE) and thermomagnetic phenomena. We also examine the Nernst-Ettingshausen effect (NE) in topological insulators and superconductors, revealing the influence of band topology and vortex-like excitations. Special attention …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 3, 2024 · pp. 1–5 Read article
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Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device
Abstract: This paper emphasis on the design, fabrication and analysis of 45 nm P type MOSFET device using SILVACO TCAD tool. The analysis was based on variation of various parameters like oxide thickness, threshold implant and halo implant (pockets) to analyze the threshold voltage. The drain versus gate and drain versus gate plots are being plotted using tony-plot. It has been observed that as the thickness of the oxide increases, threshold …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 13–20 Read article
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Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device
Abstract: This paper emphasis on the design, fabrication and analysis of 45 nm P type MOSFET device using SILVACO TCAD tool. The analysis was based on variation of various parameters like oxide thickness, threshold implant and halo implant (pockets) to analyze the threshold voltage. The drain versus gate and drain versus gate plots are being plotted using tony-plot. It has been observed that as the thickness of the oxide increases, threshold …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 13–20 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article