Search
20 articles for “Flip-flops”
-
Implementation of Sense Amplifier-based D Flip-Flop using 0.25 µm and 0.18 µm Technology
Abstract: The traditional flip-flops and latches suffer from the large delays and the race conditions. This paper describes a new approach to the D flip-flop design using the sense amplifier. The previous efforts in the same direction made at the 0.25 µm technology exhibit improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops. The paper discusses the flip-flop at 0.18 µm technology. The output latch of …
Published in Journal of Electronic Design Technology · Vol. 4, Issue 3, 2013 · pp. 10–13 Read article
-
Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element
Abstract: Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge frequencies. To lower its latency, the C-element has additionally …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 36–44 Read article
-
Ultra Low-Power 9-Transistor Flip-Flop Design
Abstract: AbstractThe use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate. The challenge for VLSI technology is mainly in leakage power consumption. Flip-Flops (FFs) are the basic storage elements used extensively in digital system designs. It accounts for 20%–45% of the total system power and may considerably impact the chip area. In this paper, an ultra-low-power true …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 27–32 Read article
-
A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology
Abstract: Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption as compared to the other CMOS design styles. This paper proposes a novel high speed flip flop design in 16 nm technology. The design was compared with the existing low power techniques in terms of power, and delay (clk-Q and D-Q). The proposed design was found to be 20% fast as compared to basic 9T …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 37–44 Read article
-
Study and Analysis of Digital Counters for VLSI Applications
Abstract: AbstractThe counter is a fundamental and essential component. It is used in most digital devices. A counter is a sequential circuit that is used as a counter. The counter is the most widespread application of flip-flops. It is a group of flip-flops in which a clock signal is placed. A counter stores the number of processes related to a clock. It is classified into two categories. The number of flip-flops …
Published in Recent Trends in Programming languages · Vol. 7, Issue 3, 2020 · pp. 17–24 Read article
-
Tunable optomechanical induced transparency and Fano-resonance in double cavity Optomechanical system with nonreciprocal coupling
Abstract: We explore theoretically optomechanical induced transparency and asymmetric Fano-Line shape profile of a double cavity optomechanical system with nonreciprocal coupling at weak and strong coupling regime. The model system consists of one mechanical mode and two optical modes. The optical mode is coupled via nonreciprocal transition. The mechanical model is coupled to the optical model via optomechanical interaction. We have analyzed induced transparency and Fano-Line shape profile and present a …
Published in Research & Reviews : Journal of Physics · Vol. 10, Issue 2, 2021 · pp. 5–15 Read article
-
Numerical Simulation of Low Reynolds Number Incompressible Flow over Two Side-by-Side Circular Cylinders
Abstract: A second-order accurate unstructured collocated implicit finite volume method based on the primitive-variable formulation is used to study the flow field around a pair of cylinders arranged in side-by-side configuration. Numerical simulations are carried out for long time on a high-resolution mesh to obtain the appropriate evolution of the overall flow field and vortex structure of the wakes. A wide range of gaps between the cylinders is considered over a …
Published in Journal of Aerospace Engineering & Technology · Vol. 3, Issue 3, 2013 · pp. 22–51 Read article
-
MAC Unit Implementation on FPGA
Abstract: Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 29–37 Read article
-
Review of Low Power Johnson Counter
Abstract: Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 13–17 Read article
-
Low Power and High Speed Techniques for Sequential Circuits
Abstract: This paper proposes techniques like MT-CMOS, power gating, dual stack, Galeor and Lector to reduce the leakage power. A D-Flip Flop has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of D Flip Flop. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a …
Published in Journal of Power Electronics and Power Systems · Vol. 4, Issue 3, 2014 · pp. 41–45 Read article
-
Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Abstract: This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 53–61 Read article
-
An Efficient Counter Using Modified Upper and Lower SVL Techniques and TSPCL
Abstract: Low power VLSI has emerged as the fundamental building block of the modern electronic era. This leads to a substantial paradigm shift where both power dissipation, performance and area of utmost importance. In the earlier time of fabrication, power dissipation was mainly neglected due to low device density and low operating frequency needed for computation. But in modern technological era, the need for high device density, higher operating frequency, proliferation …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 37–43 Read article
-
Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic
Abstract: Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 21–28 Read article
-
Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits
Abstract: This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 · pp. 30–42 Read article
-
Analysis of LSDCCFF at 0.09 µm Technology
Abstract: The traditional low swing differential conditional capture flip-flop (LSDCCFF) for LC resonant clock distribution network has wide range of applications but has poor power consumption. These characteristics can be improved by using the modified LSDCCFF. This paper presents the design of modified LSDCCFF with less delay and low operating power. The implementation of the circuit is done using LSDCCFF. By using voltage scaling technique, the average power consumption can be …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 2, 2014 · pp. 32–39 Read article
-
Power-Efficient Design Strategies for Static Random Access Memory with Memory Blocks: A Review
Abstract: For many years, CMOS technology has been able to achieve high integration density and great performance by scaling down its feature size and threshold voltage. Power consumption has been a major concern in VLSI design due to the ongoing drop in aspect ratio and the related improvements in chip density and operation frequency. SRAM is a type of random-access memory in which an interruption in power causes data loss. For …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 3, 2023 · pp. 23–32 Read article
-
Design of Digital Frequency Sensitive Phase Detector and study its Phase Response
Abstract: In this paper, a digital frequency sensitive phase detector (PD) with voltage controlled phase response is presented. This scheme is based on classical type flip-flop phase detectors and an improved PD operating on both edges of the input sequence. Phase-to-voltage response characteristic control is accomplished by the additional feedback of the low-pass filter output voltage to reset the control pin input. In this paper, we have presented a simulated frequency …
Published in Journal of Microwave Engineering and Technologies · Vol. 8, Issue 3, 2021 · pp. 43–51 Read article
-
VLSI Implementation of Bit/Digit Serial-Parallel Finite Field GF (2m) Multiplier Using Standard Basis
Abstract: A Finite Field is a field with finitely number of elements. It is also known as Galois field in which the elements can take q different values is referred as GF (q).Finite fields are of great interest in applications like Elliptic Curve Cryptography (ECC), error control and coding. In this paper, we present a simple implementation of finite field GF (2m) multiplier. Here the main aim is to enhance the …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 3, 2014 · pp. 1–6 Read article
-
Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter
Abstract: Circular retiming improves performance and power consumption of the Least Mean Square (LMS) adaptive filter. It is implemented for weight updated block and error computational block to minimize the adaptive filter error without violating the functional equivalence output. Here, filter multiplication block is updated in a circular convolution format and is retimed to reduce the dynamic power consumption. Additional retime flip-flops shows better performance result compared with the existing state-of-the-art …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 1–9 Read article
-
Hardware/Software Co-Simulation of Gradient-based Edge Detectors: A Comparative Study
Abstract: Edge detection, a segmentation technique, produces an edge map that contains important information about the image. We realized Gradient-based Edge Detection Algorithms in FPGA hardware utilizing Hardware-Software Co-Simulation with the help of Simulink (Mathworks) and System Generator (Xilinx). We explored and utilized different gradient based edge detection operators Sobel-Fieldman, Robert and Prewitt Operator. After comparative analysis, we found both Sobel and Robert operators among the best with hardware realization of …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 2, Issue 3, 2015 · pp. 30–37 Read article