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17 articles for “FPGA Implementation”
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MAC Unit Implementation on FPGA
Abstract: Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 29–37 Read article
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Automatic Coffee Making Machine Using Verilog HDL
Abstract: This Paper focuses on the design and implementation of a Coffee Machine using Verilog, aimed at understanding how real-life machines can be controlled using digital logic. In daily life, a coffee machine works by taking user inputs, processing them, and giving the required output such as preparing coffee. The main objective of this project is to design a simple digital system that controls the basic working of a coffee machine. …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 1, 2026 · pp. 18–24 Read article
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Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article
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Design of a Verilog HDL-Based Advanced Intelligent Automatic Railway Gate Control System
Abstract: Human mistake, sluggish reaction times, and manual gate operation are common causes of railway level crossing accidents. This project suggests an Intelligent Automatic Railway Gate Controller made with Verilog HDL and simulated in Xilinx Vivado to lessen these mishaps. With the goal of improving safety at unmanned railway crossings, the system is intended to offer a dependable and entirely automated solution. Without human interaction, the railway gate is automatically controlled …
Published in International Journal of Electronics Automation · Vol. 4, Issue 1, 2026 Read article
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Verilog-Based Image Processing on Field Programmable Gate Arrays: Design and Implementation
Abstract: Integrated circuits known as Field Programmable Gate Arrays (FPGAs) are frequently offered for sale off the shelf. They are known as "field programmable" because, following manufacture, they enable users to modify the hardware to satisfy particular use case needs. This makes it possible to update features and correct bugs in-place, which is very helpful for remote deployments. Configurable logic blocks (CLBs) and a series of programmable interconnects are features of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 13–26 Read article
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A Review on Two-Wheeled Self-Balancing Robot Using Spartan-3E FPGA for Sensor Fusion and Real-Time Motor Control
Abstract: Two-wheeled self-balancing robots (TWSBR) are a popular application of embedded control and robotics because they operate on the inverted pendulum concept, which is naturally unstable. The main objective of such robots is to continuously maintain balance by estimating the tilt angle and applying corrective motor action in real time. In most practical systems, low-cost inertial sensors such as accelerometers and gyroscopes are used for tilt measurement. However, accelerometer readings are …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 17–27 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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FPGA Enabled Flight Control Unit
Abstract: The FPGA flight controller revolutionizes drone technology with unmatched stability and precision. Integrated with an IMU and advanced sensors like the MPU 6050, it ensures accurate positioning critical for reliable UAV operation. Its efficient real-time data processing and seamless sensor communication enhance performance and reliability across various conditions. This advancement sets a new standard in UAV technology, suitable for applications ranging from surveillance to disaster relief. An aircraft's flight control …
Published in Journal of Aerospace Engineering & Technology · Vol. 14, Issue 1, 2024 · pp. 19–25 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
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Designing Digital Filters of Underwater Wireless Sensor Node
Abstract: Underwater Wireless Sensor Networks (UWSNs), an emerging area, integrate sensing, computing, and communication into a single compact device. The digital data is acquired using an FPGA (Field Programmable Gate Array), and the fusion of numerous sensor data is accomplished in the sensor node’s ARM (Advanced RISC Machine) CPU. The sensor interfacing circuit should connect the sensor to the sensor node’s data collecting system. The data from these sensors may be …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 43–53 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article
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VLSI Based Traffic Light Controller
Abstract: This study details the development and realization of an advanced traffic light control system utilizing VHDL (Very High-Speed Integrated Circuit Hardware Description Language) in conjunction with FPGA (Field Programmable Gate Array) technology. The system is designed to regulate a four-way intersection, with one primary high-traffic road intersecting with a less congested side road. To enhance traffic efficiency and minimize idle times, the model incorporates intelligent features such as a vehicle …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 2, 2025 · pp. 40–47 Read article
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Performance Analysis of AES Encryption Using LFSR-Based Key Expansion in VLSI
Abstract: Secure data transmission has become increasingly important with the rapid growth of digital communication and embedded systems. Protecting sensitive information from unauthorized access requires reliable cryptographic solutions. Among the available techniques, the Advanced Encryption Standard (AES) is widely recognized for its strong security and efficient implementation in both hardware and software environments. In this work, the design and performance evaluation of an AES-based crypto processor with LFSR-driven key expansion is …
Published in Recent Trends in Electronics Communication Systems · Vol. 13, Issue 1, 2026 Read article
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Power Estimation Approach for Artix 7 FPGA using Machine Learning Technique
Abstract: This paper presents the power estimation approach using a suitable machine learning technique. Artix7 FPGA has been chosen as the target FPGA (Field Programmable Gate Arrays) platform for understanding the methodology of power estimation. There are various approaches of power estimation for FPGAs that have been given in the literature viz. probabilistic, statistical, and LUT- based, etc. In the past few years, the demand for hand-handled devices like smartphones, tabs, …
Published in Research & Reviews: A Journal of Embedded System & Applications Read article
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Hardware Synchronization for Embedded Multi-core Processors
Abstract: The focus is not on whether multi-core systems are becoming prevalent, but on how microcontroller architectures should be designed to comply with stringent field requirements. This paper illustrates the transition from single to multiple cores, ensuring coherence and consistency in shared memory through hardware mechanisms. Hardware barriers are implemented to allow for point-to-point synchronization between processor cores. Practical experiments center on the initial stages of transforming single-core systems into dual-core …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 33–42 Read article
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Design and Implementation of Low Latency 16-bit Full Adder
Abstract: In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing and systems play a vital role in the analysis and computation of data representation. Electronic systems have gradually become faster and smaller scale. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 21–31 Read article