Search
153 articles for “CMOS design”
-
Design And Validation of High Efficiency Of 10T Sram with High Recoverability Of Multi Node Soft Error
Abstract: Sensitive nodes' critical charge is decreasing, which increases the soft-error vulnerability of SRAM cells used in aerospace applications. A single event upset (SEU) occurs when a radiation particle hits a sensitive node in a typical 6T SRAM cell, flipping the data that has been stored in the cell. Consequently, a Soft-Error-Aware Read-Stability-Enhanced Low Power 10T (SARP10T) SRAM cell is suggested in this project to reduce SEUs. The quadro cell exhibits …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 2, 2024 · pp. 7–14 Read article
-
Performance Analysis of DG FinFET for Ultralow-power Subthreshold Applications
Abstract: Subthreshold operating region of transistor shows huge potential toward satisfying demand of ultralow power (ULP) consumption from handheld portable devices. However, operating device with such small subthreshold leakage current as a switching current gives huge penalty in their operating frequency. For subthreshold operating region key design goal is to boost the speed of the device. DG FinFET device shows excellent device characteristics in subthreshold operating region. In this paper, 1-bit …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 26–33 Read article
-
Design of High-Speed and Low-Power Carry Skip Adder
Abstract: In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 35–44 Read article
-
Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology
Abstract: A low Off-Set high-speed two-stage dynamic comparator is presented in this paper. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 21–27 Read article
-
Design and Verification of Low Power High Speed Voltage Level Shifter Based on Pass Transistor Methodology
Abstract: This study explains how a voltage level shifter (LS) can be built using a Wilson current mirror level shifter (WCMLS) with a mirrored output. The proposed fix avoids WCMLS's typical issue of requiring a mirror with a size ratio that is too large. It's a space- and cost-saver. The proposed LS requires less components than its modern versions and uses only tiny components, taking up even less space. The proposed …
Published in Journal of Control & Instrumentation · Vol. 14, Issue 2, 2023 · pp. 30–37 Read article
-
High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator
Abstract: This paper comprises a novel fully differential double tail high performance comparators suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the requirement of high speed, low power consumption with low offset voltage. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in TSMC 180nm technology with ±0.9V supply. The proposed …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 7–16 Read article
-
Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review
Abstract: Nanowires are inimitable materials for considering phenomenon in nanoscale regime. Nanowires development exhibits ample of applications by controlling their, structure, composition as well as their electrical properties. This paper review diverse types of nanowires, nanowire field-effect transistor (NWFET) structure and their comparison with novel devices. Firstly, this paper describes different types of nanowires and nanowire heterostructure that shows nanowire heterostructures eliminates various factors that limit the performance of homogeneous nanowire …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 19–32 Read article
-
A Study on Polymer-Based FinFET Applications and Logic Circuit Implementation with FinFET
Abstract: Nano devices play a crucial role in the semiconductor industry and can work as the solution for the problems like scaling of MOSFET. The FinFET can serve as the substitute of bulk CMOS in nanoscale. It mainly consists of two gate terminals which can be either shorted or kept independent.The shorted gate (SG-FinFET) configuration provides higher Ion and Ioff whereas the Independent Gate (IG-FinFET) configuration reduces the transistor count and …
Published in Journal of Polymer & Composites · Vol. 13, Issue 1, 2025 · pp. 312–340 Read article
-
CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.
Abstract: Analog computing techniques are gaining attention for machine learning (ML) applications due to their ability to reduce computational complexity. Continuous operations such as addition and subtraction offer a simpler and more efficient approach compared to probabilistic product decoding, which can be sensitive to noise and inconsistent measurements. This paper presents a simulated VLSI implementation of a broadcast edge connection, independent of the MOS component model, along with experimental results. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 8–17 Read article
-
Automated Headlight Intensity Controller and Speed Control in Vehicles
Abstract: AbstractHeadlight intensity of vehicles poses a great danger during night travel. The drivers of most vehicles use high bright beam while driving at night. This causes inconvenience for the person travelling from the opposite direction. Person experiences a sudden blaze for a short duration. When these headlights shine brightly, they cause a temporary blindness to a person, resulting in road accident during night. To avoid such incidents, we are designing …
Published in Journal Of Network security · Vol. 7, Issue 2, 2019 · pp. 1–5 Read article
-
Employment of Solid-State Technology in Sensor Design: A Study
Abstract: The rapid evolution of sensor technologies has been driven by the demand for more precise, durable, and compact systems to meet the needs of modern industries, healthcare, and consumer electronics. Solid state technologies have emerged as a transformative force in sensor design, offering unprecedented performance, reliability, and integration potential. Unlike traditional sensors, which often rely on mechanical, electrochemical, or piezoelectric principles, solid state sensors leverage the intrinsic properties of materials …
Published in International Journal of Solid State Innovations & Research · Vol. 3, Issue 2, 2025 · pp. 31–41 Read article
-
Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power
Abstract: This paper presents the analysis and characterization of various topologies of dynamic latch based complementary metal oxide semiconductor (CMOS) comparator. Various comparator topologies like resistor divider comparator (RDC), differential pair comparator (DPC), double-tail dynamic latched comparator (DTDLC), energy efficient two-stage comparator (ETWC) and two-stage dynamic comparator (TSDL) are analyzed and compared for various performance parameters. Besides zero static power consumption, resistor divider comparator has high offset voltage and it depends …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 86–98 Read article
-
Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips
Abstract: At lower nodes of complementary metal-oxide semiconductor (CMOS) technology, noise within a chip increase due to a drastic increment in interconnects within a given area. To improve the noise immunity of a chip, a Schmitt trigger circuit is used as a buffer instead of a simple CMOS inverter at various intervals along the metal interconnect. The use of a Schmitt trigger circuit not only makes the chip noise immune but …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 11–20 Read article