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204 articles for “comparator circuit”
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Hidden Buck Chopper Circuits Topology in a Switch Controlled Singe Phase Rectifier, Size and Cost Analysis
Abstract: This paper shows hidden buck chopper circuits topology in a single phase switch controlled full wave rectifier. Justification of this realization yields the opportunity to use the single circuit structure for both AC to DC and DC to DC conversion processes. Generally, two diodes out of four diodes are replaced by two switches to offer voltage gain and input power factor regulation in a single phase full wave rectifier. Such …
Published in Journal of Power Electronics and Power Systems · Vol. 5, Issue 2, 2015 · pp. 17–28 Read article
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Performance Analysis of Fe/SiO2/Fe MTJ and Ni/Al2O3/Ni MTJ-based Magnetoresistive Random Access Memories (MRAMs)
Abstract: This paper reports the first principle simulations of Fe/SiO2/Fe and Ni/Al2O3/Ni magnetic tunnel junctions (MTJs). A performance analysis has been done based upon the device-level simulations of the two magnetic tunnel junctions followed by the circuit level simulations of magnetoresistive random access memory (MRAM) cell operating with the two MTJs respectively. From the device-level simulations, the two MTJs have been compared with regard to the bias dependence of TMR ratios, …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 92–100 Read article
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Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology
Abstract: Objective of this paper is the analysis of voltage buffer and is referred to as a common drain amplifier or that can be considered as a source follower also. It compares the result of simple voltage buffer that results with the memristor inbuilt in the same schematic circuit of voltage buffer. Memristor is considered as a fourth existing component after the resistor, capacitor and an inductor proposed by Dr. L.O. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 62–72 Read article
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Cold Light Source for Endoscopy using AVR Microcontroller
Abstract: An endoscopy involves the procedure of examining internal organs of the human body using endoscope. Presently, during endoscopy halogentype or xenon type light sources are used. The main drawback of these sources is the heat dissipated by them effects the sensor data. Due to high temperature in the surrounding environment, the video tube or optical fiber used to transfer data may be damaged. Moreover if the lamp turns off during …
Published in Journal of Control & Instrumentation · Vol. 5, Issue 1, 2014 · pp. 5–10 Read article
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Comparative Assessment of Polymers and Composites for Solar Panels: Fundamentals, Performance Metrics, Manufacturing, and Sustainability
Abstract: This paper presents a comprehensive review of the main types of Photo Voltaic polymers and composites such as crystalline silicon (both mono- and poly-Si), thin-film tech (CdTe, CIGS, a-Si), perovskites, and organic/dye-sensitized cells and analyses the parameters such as efficiency, fill factor, open-circuit voltage, temperature response, and degradation. The analysis focusses on polymers and composites and manufacturing techniques like vapor deposition, roll-to-roll printing, and both solution and vapor techniques for …
Published in Journal of Polymer & Composites · Vol. 14, Issue 3, 2026 · pp. 120–130 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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Three Stage High Step-up Interleaved Boost Converter with Voltage Multiplier Cell
Abstract: In this paper, three stage high step-up interleaved boost converter with three voltage multiplier cells (VMCS) and three state switching cells (3SSC) is proposed. Here an interleaved boost converter is used, as a result higher efficiency and reduced input ripple current is obtained. Also, an additional stage of voltage multiplier i.e., three stages is added so that voltage gain will increase. It reduces switching loss and stress through the devices. …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 39–56 Read article
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Power Reduction at 90 nm through Circuit Level Modification
Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article
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Analysis and Comparison of Space Vector and Sinusoidal PWM Controlled Two Level Inverter Fed 3- Induction Motor
Abstract: The current generation of variable speed drives is typically based around the real-time digital generation of Pulse-Width Modulated (PWM) waveforms using either microprocessors or application-specific integrated circuits in many ways. PWM generation techniques for getting the control of inverters have the major advantages that component drift and tolerance problems associated with earlier analog implementations. Of all the various PWM techniques Sinusoidal and Space vector PWM techniques are more prominent. The …
Published in Trends in Electrical Engineering · Vol. 3, Issue 1, 2013 · pp. 1–11 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Fabrication, Numerical Simulation and Compact Modeling of Ph-BTBT-C10 Organic Thin Film Transistor
Abstract: Flexible and cost-effective electronics have been necessitated by the advent of organic thin-film transistors (OTFTs). This study aims to study the performance of OTFT using a 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C10) organic semiconductor. The paper also explore accurate device modeling for technology optimization and circuit design that supports device improvement. This research includes device fabrication, numerical simulation using TCAD, compact modeling, and parameter extraction. By combining temperature-dependent bandgap narrowing with existing theories, this …
Published in Journal of Polymer & Composites · Vol. 12, Issue 5, 2024 · pp. 1–18 Read article
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Wireless Annunciator Window for Substation Application with GSM Facility
Abstract: The work aim is to understand and design of wireless communication between annunciator window and circuit breaker, relay, transformers etc. located in switchyard of power substation. The wireless communication methods are more reliable, convenient, economical, and faster as compared to the actual wire communication system. In this paper, we have used a GSM system for sending wireless signal to the annunciator window. GSM system supports to transfer the information over …
Published in Journal of Power Electronics and Power Systems · Vol. 7, Issue 1, 2017 · pp. 22–27 Read article
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Current Controlled Oscillator Using FinFET
Abstract: A current-controlled oscillator using 18 nm FinFET technology is proposed in this study which consists of a Current Controlled Differential Difference Current Conveyor (CCDDCC) block to control the current. FinFET technology has better scalability and lower leakage current compared to traditional CMOS, which allows it to surpass the obstacles faced by CMOS-based oscillators. The suggested oscillator is suitable for electronic applications such as Phase-Locked Loop (PLL) systems, radio frequency (RF) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 3, 2025 · pp. 17–28 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Compact MIMO Antenna Array based on Koch Fractal Metamaterial for 5G Applications
Abstract: In this paper, a design of a printed MIMO antenna array for 5G applications is proposed based on low profile structure. Thus, the antenna element is designed as a printed mender monopole with a partial ground plane. The partial ground plane is proposed to realize bandwidth enhancements through etching rectangular slots in the antenna back panel. It is found that such antenna shows two frequency bands, S11<-10dB, from 3 GHz …
Published in Journal of Microwave Engineering and Technologies · Vol. 9, Issue 3, 2022 · pp. 1–7 Read article
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High-speed CMOS ADCs Design
Abstract: This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 59–74 Read article
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Designing of Low Power Charge Pump Circuit with Minimum Current Mismatch for High Speed PLL Applications
Abstract: Charge pump (CP) is one of the necessary block of phase locked circuit (PLL). This paper presents the new design of CP circuit, i.e., cascode current source biased transmission gate based CP circuit. Cascode current mirror, transmission gate switches and unity gain follower amplifier are combined to design the CP circuit in 65 nm technology. The reference current is used to bias the switches of CP circuit so that current …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 1–8 Read article
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design
Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article