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193 articles for “transistor”
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Design and Implementation of Low Power and High Speed 10T SRAM with High SNM
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell utilizes a strong cross-coupled structure that combines a standard inverter with a stacked transistor and a Schmitt-trigger inverter with a double-length pull-up transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 40–65 Read article
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Analysis of DIBL Effect in MOSFET Working
Abstract: AbstractOne of the most widely used electronic devices, particularly in digital integrated circuits, is the metal insulator semiconductor (MIS) transistor. Most of the existing transistors used in fabrication of integrated chips are with junctions. The device scaling is growing the channel length between junctions in devices are scaling gone down to 10 nm. Drain Induced Barrier Lowering (DIBL) effect is prominent as the feature size of MOS device keep diminishing. …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 33–40 Read article
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MOS Capacitor: A Processing Tool
Abstract: In this modern world of technology, life without electronics is unimaginable. We are now living in the age of electronics. It is hard to find an electrical item in your home that does not have electronics part in it. The electronic devices give better efficiency and reliability in terms of power loss, speed and cost; the fundamental component of each Integrated Circuit (IC) chip, namely the MOSFET (metal oxide semiconductor …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 27–32 Read article
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Implementation and Analysis of Full Adder using low Power Adiabatic Techniques
Abstract: AbstractIn this study, authors have discussed, designed and compared the low power adiabatic logic energy efficient recovery logic (ECRL) and positive feedback of adiabatic logic (PFAL) with conventional Complementary Mosfet (CMOS) logic. A one-bit full adder using these design techniques are implemented and results are compared like power, delay, transistor count and power delay product. Tanner tool v13 is used for designing of schematic and simulation. From the result, it …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 1–8 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 28–34 Read article
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Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques
Abstract: In the last few decades, due to the ever growing demand for portable and small sized devices, integrated circuits require electronic circuit design methods to implement integrated circuits with low power consumption. The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Adiabatic logic technique is one of the …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 30–33 Read article
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Review Paper To Design a Low Power CNTFET Based XOR Gate
Abstract: The continuous scaling down of Silicon technology leads to various critical challenges and reliability issues such as short channel effect, high leakage current, interconnect problems, etc. CNTFET is the most probable substitutes to traditional MOSFET. The CNTFET device based circuits portray advantages with its better control over the device channel, reduced leakage current, reduced short channel effects. The CNTFET based XOR gate circuits incur the minimum power and energy dissipation. …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 48–53 Read article
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Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique
Abstract: Single-electron transistors (SETs) are an attractive candidate for future functional elements in LSIs, because of their low-power consumption and small size. Integration of current CMOS technology with the emerging SET devices is an effective approach for improving density of integration in VLSI chips and ensuring ultra low power dissipation along with the advantages of CMOS technology like high gain, current drive, speed and matured fabrication technology. This paper investigates hybrid …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 24–29 Read article
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Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Nonlinear Semiconductor Device Modeling using Neural Networks
Abstract: This paper describes the nonlinear semiconductor (transistor) of small and large signal modeling using a single neural network. Multilayer perceptron (MLP) with back-propagation (BP) learning is adopted in this work to model the drain current (ID) and the transconductance (gm) of the transistor. MLP modeling performance in terms of mean square error (MSE) and complexity of the network are illustrated briefly. Artificial neural network (ANN) model outcome for nonlinear function …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 1–6 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 28–34 Read article
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A Reliable Low Standby Power 6T SRAM Cell
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 33–59 Read article
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Reduce the Leakage Current and Power in VLSI Technology
Abstract: Demand for portability Reduce and increase in size, low cost, low dynamic power, low leakage current, low sub threshold current, and the necessity to minimise at least one of these. Circuit complexity increases with circuit integration. Memory and microprocessors are included in mass-produced chips. Microcomputer systems central system memory uses dynamic random-access memory (DRAM). One benefit of DRAM memory is its high speed and capacity integration. The examination of DRAM …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 3, 2023 · pp. 19–25 Read article
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High Frequency Design Approach and Feasibility Study of HBT Based W-band (90.0 GHz-100.0 GHz) Amplifier using 130 nm SiGe Based BiCMOS Technology
Abstract: This paper present high frequency design approach and feasibility study of HBT (Hetero Junction Bipolar Transistor) based two-stage cascode amplifiers at W-band (90.0 GHz-100.0 GHz). The proposed amplifier has design using 130 nm SiGe based BiCMOS technology. This paper used low cost technology for designing of w-band amplifier and this is novelty of this paper. The schematic design and feasibility study has been carried out using Cadence software. The selection …
Published in International Journal of Digital Communication and Analog Signals Read article
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Design and Simulation of LNA in 90 nm CMOS Technology for Radio Receiver using the Cadence Simulation Tool
Abstract: Due to its successful operation in the 2.4 GHz frequency region, often known as the ISM (Industrial, Scientific, and Medical) band, RFICs play a vital role in communication systems. The major parts being used transceivers for frequency translation and amplification are LNA and Mixers. Different types of mixers and LNAs are employed, and different strategies are used to optimize them. In this paper an approach for design and simulation of …
Published in International Journal of Digital Communication and Analog Signals Read article
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Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET
Abstract: we carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k. Based on device simulation we find that the asymmetric oxide …
Published in Journal of Semiconductor Devices and Circuits Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article