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156 articles for “gating design”
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Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design
Abstract: Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 15–20 Read article
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Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers
Abstract: VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 32–36 Read article
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A Neuromorphic-Inspired, Low-Power VLSI Architecture for Edge AI in IoT Sensor Nodes
Abstract: As the proliferation of Internet of Things (IoT) devices continues to rise, there is an increasing demand for real-time, energy-efficient artificial intelligence (AI) processing directly at the network edge. Traditional edge AI accelerators, often based on deep learning models like convolutional neural networks (CNNs), struggle to meet the ultra-low-power requirements of battery-constrained IoT sensor nodes. In response to this challenge, this study introduces a neuromorphic-inspired, low-power very- large-scale integration (VLSI) …
Published in Journal of Microelectronics and Solid State Devices · Vol. 12, Issue 2, 2025 · pp. 41–47 Read article
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Layout Design, Fabrication and Characterization of n-Channel MOSFET
Abstract: Primary force behind evolution of semiconductor industry is MOSFET, after its first IC based experimental demonstration in 1960s. It is fundamental working unit of most of the electronic circuits like cells in living being. Number of devices on a single chip has been increased with rapid phase with evolution of new technology of materials. Today there are more than 4 billion transistors are there on a single chip with effective …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 13–18 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Impact of Source/Drain Engineering on Performance of Single Gate and Dual Gate Junctionless MOSFET
Abstract: Abstract: This letter is the study on impact of source/drain engineering on Single Gate (SG) and Dual Gate (DG) Junctionless MOSFET. Both the proposed MOSFET have Gate Stacking and highly doped source/drain region, so name suggested is Highly Doped Source Drain Gate Stack Junctionless (HDSD-GSJL) MOSFET. Here we investigate the effect of highly doped source/drain, gate stacking and double gate on junctionless MOSFET. The investigation is performed in relations of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 10–14 Read article
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article
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Low Power and High Speed Techniques for Sequential Circuits
Abstract: This paper proposes techniques like MT-CMOS, power gating, dual stack, Galeor and Lector to reduce the leakage power. A D-Flip Flop has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of D Flip Flop. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a …
Published in Journal of Power Electronics and Power Systems · Vol. 4, Issue 3, 2014 · pp. 41–45 Read article
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Speed Measurement of Moving Object using Arduino
Abstract: This research paper presents the design, construction, and testing of a low-cost and reliable system for measuring the speed of moving objects using an Arduino micro controller. The project employs Infrared (IR) sensors as photo gates to detect the time taken by an object to travel between two fixed points, allowing the Arduino to calculate the speed using basic timing algorithms. The design provides an affordable and educational alternative to …
Published in Recent Trends in Sensor Research & Technology · Vol. 13, Issue 1, 2026 · pp. 1–8 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article
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A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing
Abstract: Modern IC technology force on the ICs design considering more area optimization and low power techniques. We study herein the effect of hetero gate dielectric materials on the OFF-current (IOFF) and ON-current (ION) of the heterogate (high-k/low-k) tunnel field-effect transistor for which the simulations give significant improvements as compared to single-gate devices using an SiO2 gate dielectric. The ambipolar behavior is suppressed and radio frequency (RF) parameters are enhanced by …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 55–66 Read article
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Experimental Investigations to Improve the Electrical Characteristics of Nitride-Based Nanoelectronic High Electron Mobility Transistors
Abstract: In this work, the DC and RF performances of conventional nanoelectronic high electron mobility transistor (HEMT) are compared with those of two individually modified HEMT structures in a nano-scale regime. All simulation results are produced by the SILVACO- ATLAS physical simulator according to the performed designs of HEMT structures. In each of these HEMT structures, the formation of quantum well is demonstrated at unbiased condition. In the DC analysis of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 1, 2021 · pp. 14–30 Read article
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Designing Digital Filters of Underwater Wireless Sensor Node
Abstract: Underwater Wireless Sensor Networks (UWSNs), an emerging area, integrate sensing, computing, and communication into a single compact device. The digital data is acquired using an FPGA (Field Programmable Gate Array), and the fusion of numerous sensor data is accomplished in the sensor node’s ARM (Advanced RISC Machine) CPU. The sensor interfacing circuit should connect the sensor to the sensor node’s data collecting system. The data from these sensors may be …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 43–53 Read article
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FPGA Implementation of LDPC Codes
Abstract: AbstractLow Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 21–28 Read article
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Simulation Studies on the Electrical Characteristics of High Electron Mobility Transistors
Abstract: AbstractSimulation studies have been performed on the AlGaN/GaN high electron mobility transistor (HEMT) with AlN spacer layer. The current-voltage characteristics have been studied with respect to different gate voltages and different doping concentrations. Studies have been performed on the quantum well depth variation corresponding to the designed HEMTs.Keywords: Doping, drain current, drain voltage, quantum wellCite this ArticleSanjib Kalita, Ashish Prajapati, Susanta Sinha Roy, Jyoti Prasad Banerjee, James Andrew McLaughlin, Subhadeep …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 2, 2016 · pp. 32–36 Read article
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Detection of Fault and Protection of Faulted Distribution Feeder with Field Programmable Gate Array Using State Diagrams
Abstract: A hardware-efficient algorithm for fast fault-detection in feeders radiating out of a distribution substation and its subsequent clearance from the system for safe operation of the healthy parts has been presented in the paper. State diagrams used to design the circuit.The general purpose SPARTANE 3AN FPGA kit has been employed for developing the protective over-current relay. All the coding has been done using the hardware description language VERILOG. To avoid …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 5–12 Read article