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190 articles for “VLS”
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Efficient Design of Pseudo-Random Pattern Generator with High Fault Coverage
Abstract: In this paper a comparative analysis of various test pattern generators is done in terms of power consumed .Testing is a crucial process in VLSI (Very-large-scale integration), not only it ensures proper functioning of the chip ,it also helps identify the common faults that occur as a part of VLSI fabrication. However, the power consumed during the testing process is nearly 40% higher than normal circuit operation. Various test pattern …
Published in Journal of Microelectronics and Solid State Devices · Vol. 1, Issue 1, 2015 · pp. 21–25 Read article
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Ternary Logic Design Approach - From CMOS to CNTFET
Abstract: The goal of this review is to offer a broad study on the ternary logic designs based on CMOS (complementary metal-oxide-semiconductor) and CNTFET (carbon nanotube field effect transistor) suitable for energy efficient and high-performance VLSI design. Performance investigation of the ternary logic-based designs will be the primary emphasis as the ternary logic is a good substitute for the conventional binary logic among all the multiple-valued logics because it permits simple …
Published in Journal of Nanoscience, NanoEngineering & Applications · Vol. 8, Issue 2, 2018 · pp. 20–30 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.
Abstract: Analog computing techniques are gaining attention for machine learning (ML) applications due to their ability to reduce computational complexity. Continuous operations such as addition and subtraction offer a simpler and more efficient approach compared to probabilistic product decoding, which can be sensitive to noise and inconsistent measurements. This paper presents a simulated VLSI implementation of a broadcast edge connection, independent of the MOS component model, along with experimental results. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 8–17 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Silicon Symphony: The Science of Semiconductors Circuits
Abstract: Modern electronics are built on the foundation of semiconductor circuits, which precisely and efficiently control the flow of electrical impulses. This article takes a look at the underlying physics of semiconductor materials and how their unique electrical properties allow the design and functioning of diodes, transistors and integrated circuits. This study links microscopic scientific principles to the behaviour of real circuits. It considers essential concepts such as charge carriers, doping …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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Low Power Area Efficient 4×4 Vedic Multiplier using GDI half adders with Better Delay Performance
Abstract: In the field of VLSI, wireless communication and digital signal processing, low power and area efficient architectures are considered. Majority of such applications uses multiplication. The multiplication is done using repetitive addition and shift and add method. It consumes more area delay and power. Vedic multiplier is one of the efficient multiplier. It is designed using different Vedic techniques or sutras, which reduces the area, power consumption and provide better …
Published in Journal of Control & Instrumentation · Vol. 10, Issue 2, 2019 · pp. 28–39 Read article
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FDTD-based Time Domain Analysis of CMOS Gate Driven Interconnects
Abstract: Accurate time domain analysis of CMOS gate driven interconnects is important for the design and analysis of high performance VLSI systems. Conventionally, CMOS driver is approximated as a constant resistance instead of non-linear and time-varying MOS resistance, which causes inaccurate modeling of CMOS driver. This paper presents a new method for FDTD-based transient analysis of CMOS gate driven interconnect line using a generalized model. The generalized model of CMOS inverter …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 16–21 Read article
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1-Bit Full Adder's Analysis and Comparison
Abstract: The full adder circuit forms the basis of majority of digital circuits. Improvement in a basic full adder circuit in terms of area, power and delay affect the performance of whole system. It becomes compulsory to investigate and analyze the performance of implementation of full adder circuit in literature, till now. In this paper, a study is carried out to look into performance parameters of full adder circuit using different …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 1–6 Read article
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Design and Analysis of Bootstrap Sample and Hold Circuit
Abstract: This paper describes the design and implementation of open-loop sample and hold-circuit using bootstrap technique, which can be used as front end sampling circuit for high-speed analog-to-digital converters. Different design criteria, viz., speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18 and 0.35 μm CMOS process. It …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 3, 2014 · pp. 7–14 Read article
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Designing and Testing of various types of SRAM topologies with 90nm Technology
Abstract: VLSI technology provides a way for designing compact devices which are useful to human for leading their day to day, the advancement in the technology provides high speed and power consuming appliances. In this category, intend to design an application with high data rate and low power, memory efficient device and Static Random-Access Memory (SRAM) is structured. Improvement in the technology comprises of scaling down the design process and impact …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 12–16 Read article
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Coded Communication Device with Hamming Code
Abstract: The field of invention is VLSI. In this invention, the authors have brought into light a coded communication device which increases the security level of the system. The tools like VHDL programming language that is VHSIC hardware description language and hamming code contributed to form the foundation of the invention. In this the authors have used transducer at input terminal whose output is given to encrypter. Similarly, at the receiver …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 14–16 Read article
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Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology
Abstract: Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 17–23 Read article
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Design and Implementation of Low Power Priority Encoder
Abstract: Nowadays, low-power devices are widely used in VLSI design technology because they can reduce power consumption and power dissipation. To achieve this, various low-power techniques are utilized to minimize device power losses. This project focuses on analyzing the performance of priority encoders in different low-power technologies for Flash Type ADC. Moreover, the power consumption of these technologies is compared with the conventional CMOS design. Each of these techniques offers distinct …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 2, 2023 · pp. 1–14 Read article
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Power-Efficient Design Strategies for Static Random Access Memory with Memory Blocks: A Review
Abstract: For many years, CMOS technology has been able to achieve high integration density and great performance by scaling down its feature size and threshold voltage. Power consumption has been a major concern in VLSI design due to the ongoing drop in aspect ratio and the related improvements in chip density and operation frequency. SRAM is a type of random-access memory in which an interruption in power causes data loss. For …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 3, 2023 · pp. 23–32 Read article
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Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics
Abstract: AbstractAdder is required for many processors designing like microprocessors, digital signal processors, image processing and various VLSI applications. The overall performance of system depends upon the adder circuits due to its presence mainly in critical paths of system. This paper presents half adder circuits using different combinational MOS logics. All the circuits were analyzed to find the most suitable circuit which consumes less power without costing the speed of the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 19–27 Read article
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Ultra Low-Power 9-Transistor Flip-Flop Design
Abstract: AbstractThe use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate. The challenge for VLSI technology is mainly in leakage power consumption. Flip-Flops (FFs) are the basic storage elements used extensively in digital system designs. It accounts for 20%–45% of the total system power and may considerably impact the chip area. In this paper, an ultra-low-power true …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 27–32 Read article
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Efficient ADP Scheme for DWT Computation
Abstract: AbstractIn this paper, the lifting and flipping scheme for discrete wavelet transform (DWT) computation and proposed an area delay efficient lifting based DWT architecture. In this computation huge number of multipliers and adders are saved when lifting based 2-D DWT architecture implemented. The derived full-parallel lifting-based 1-level 2-D DWT structure involves half number of less multiplier than the flipping-based 2-D DWT structure. Compared with the existing lifting-based structure, the proposed …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 22–26 Read article
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Implementation of UART with CALBO
Abstract: The increasing growth of submicron technology has resulted in the difficulty of VLSI testing for designers who always look for simple and cost effective logic structure to realize a complex function. Thus Automatic Testing Equipment (ATE) is becoming costly process for testing. To reduce the cost of testing the chips, Built in Self-Test (BIST) has emerged as a cheaper alternative. BIST is a design technique that allows the chip to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 6–12 Read article
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Growth Mechanism Dependent Room Temperature Electrical Properties of Complex Spinel Oxide Nanostructures
Abstract: Here we present the investigation on growth mechanism and corresponding electrical properties of complex spinel zinc stannate (Zn2SnO4) nanostructures synthesized using VLS (vapour-liquid-solid) method in a vacuum operated thermal CVD setup. GAXRD, Raman and Room temperature resistivity, mobility and carrier concentration of variety of nanostructures of Zn2SnO4 have been analysed to understand the effect plausible growth mechanism dependent properties. The corresponding role of catalyst layer thickness during growth as well …
Published in Journal of Microelectronics and Solid State Devices · Vol. 7, Issue 3, 2020 · pp. 20–25 Read article