Search
153 articles for “CMOS design”
-
Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article
-
An Overview on MOSFET based Sensor Design
Abstract: In the past two decades the MOSFET has transformed from a simple switch in digital logic to an analog powerhouse that can be cofabricated with the sensing material on a single chip. MetalOxideSemiconductor FieldEffect Transistors (MOSFETs) have silently become the beating heart of modern sensor platforms, translating the faint whispers of physical, chemical, and biological phenomena into robust electrical signatures. This abstract surveys the latest advances that have turned the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 20–26 Read article
-
A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor
Abstract: A CMOS voltage reference circuit featuring MOS transistors threshold voltage extractor has been developed. The circuit implemented using 0.35µm CMOS AMS process generates a reference of 574 mV for a power supply of 3.3V with 726µW power consumption. The circuit presents a variation of 43 ppm/ºC for the –10 to –110ºC temperature, and 18.6 dB PSRR at 1 KHz. A vital analytical approach is presented to provide a universal design …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 14–19 Read article
-
Optimization of a Digital Adder Design Using MOSFET and FinFET Technology
Abstract: AbstractIn this study, a very low power high speed Adder is presented by using short gate mode technique and voltage scaling system for FinFET. MOSFET and FinFET technique is used on 32 nm by adders which compare delay and average power. Parametric study of fins vs. power is also performed in the study. Synopsys HSPICE software is used for obtaining the simulation results. Simulation results show that low power is …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 2, 2018 · pp. 30–33 Read article
-
A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic
Abstract: Domino circuits are widely used these days in the design of modern-day microprocessors because of their high speed and less area overhead compared to static logic style. In this paper, a new domino-based 4:1 multiplexer circuit has been designed which finds extensive use in register files and execution units where large amounts of data have to be broken into smaller chunks so that the processor can manipulate it more easily …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
-
Design of Low Noise Transimpedance Amplifier using Multiple Feedback filter Topology
Abstract: This study presents the highly linear and low noise transimpedance amplifier (TIA) based on CMOS inverter as an amplifier within multiple feedback (MPFB) filter topology. Absence of complex analog circuitry and compatibility with widespread digital CMOS processes highlight this TIA topology asthe best choice in signal conditioning chains approaching analog-to-digital converters (ADCs). Special attention has been given to the TIA stability and compensation networks. Using dedicated low-dropout (LDO) regulator, the …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 1, 2022 · pp. 25–30 Read article
-
Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed
Abstract: This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 1–13 Read article
-
Performance and Analysis of 6T, 8T & 10T SRAM Cell in 28nm Technology
Abstract: Technology scaling into deep sub-micron regimes has significantly increased the design challenges of Static Random Access Memory (SRAM), particularly at the 28 nm technology node. As transistor dimensions shrink, SRAM cells become more vulnerable to stability degradation, leakage current, process variations, and reduced noise margins, which adversely affect overall memory performance and reliability. The conventional 6T SRAM cell remains widely used due to its compact structure and high storage density; …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 12–18 Read article
-
Design and Analysis of Bootstrap Sample and Hold Circuit
Abstract: This paper describes the design and implementation of open-loop sample and hold-circuit using bootstrap technique, which can be used as front end sampling circuit for high-speed analog-to-digital converters. Different design criteria, viz., speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18 and 0.35 μm CMOS process. It …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 3, 2014 · pp. 7–14 Read article
-
Automatic Gain Control Amplifier for Analog Front End in Biomedical Applications
Abstract: This paper presents the design review of feed-forward automatic gain control (AGC) amplifier to be used in analog front end of biomedical applications such as hearing aid. To make system low-power, the design of each block is optimized and all elements are realized using MOS. The whole design is simulated in LT spice IV using 0.18 µm CMOS technology and the results are presented. Keywords: Automatic gain control (AGC), biomedical …
Published in Research and Reviews : A Journal of Medical Science and Technology · Vol. 5, Issue 3, 2016 · pp. 22–26 Read article
-
Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating
Abstract: With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 · pp. 1–6 Read article
-
Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology
Abstract: AbstractThis paper presents the design and analysis of double gate FinFET complimentary pass transistor logic (CPL) multiplexer. The circuit of multiplexer (MUX) using CPL is used for comparison of performance parameters like average power consumption, rise/fall time, delay, slew rate, PDP and EDP. Multiplexer is a digital circuit, it has inputs and select line; select lines are used for select input lines to transfer data to the output end. The …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 41–48 Read article
-
Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
-
Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
-
Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 28–34 Read article
-
Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
-
Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter
Abstract: Circular retiming improves performance and power consumption of the Least Mean Square (LMS) adaptive filter. It is implemented for weight updated block and error computational block to minimize the adaptive filter error without violating the functional equivalence output. Here, filter multiplication block is updated in a circular convolution format and is retimed to reduce the dynamic power consumption. Additional retime flip-flops shows better performance result compared with the existing state-of-the-art …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 1–9 Read article
-
Design and Performance Analysis of Silicon Photonic Waveguides for High-Speed Optical Communication
Abstract: The exponential growth of data traffic in data centers and high-performance computing systems necessitates a paradigm shift from conventional electrical interconnects to high- speed, low-power on-chip optical interconnects. Silicon Photonics (SiP) is the leading platform for this transition due to its compatibility with CMOS manufacturing and the high- index contrast between silicon (Si) and silicon dioxide (SiO 2 ). This paper details the design, simulation, and comprehensive performance analysis of …
Published in International Journal of Optical Innovations & Research · Vol. 3, Issue 2, 2025 · pp. 29–37 Read article
-
Performance Analysis of 1-Bit Full Adder using GDI and CMOS Logic
Abstract: The adder is one of the most essential part in math processor, multiplier, and in various scientific applications. Full adder plays important role in multiplier architecture. In this paper a 1-bit full adder using GDI and CMOS logic has been implemented and comparative analysis has been done. The less delay and low power consumption is achieved for this implementation. This paper presents comparison of number of transistors have been used …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 18–22 Read article
-
Complementary Metal Oxide Semiconductor Readout Integrated Circuit for Imaging Applications
Abstract: In this paper presents a novel continuous-time simultaneous-readout scheme for active imaging systems based on orthogonal modulation of photo detector signals. The superimposed-continuous-time approach presented here differs from the conventional scheduled-discrete-time scheme in that the photo detector signals are summed in a common bus concurrently and then converted to voltage levels for digitization. We illustrate that our proposed architecture may be profitable. Predominantly, in solicitations, the bandwidth necessities for a …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 2, 2015 · pp. 5–8 Read article