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219 articles for “low power techniques”
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques
Abstract: In the last few decades, due to the ever growing demand for portable and small sized devices, integrated circuits require electronic circuit design methods to implement integrated circuits with low power consumption. The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Adiabatic logic technique is one of the …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 30–33 Read article
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Analysis of Low Power Data Server in Distributed Environments
Abstract: The delta air temperature of a server farm is straightforwardly connected with the proficiency of the cooling framework. In the event that the temperature can be raised without critical adverse consequences on the power utilization and lifetime dependability of the IT supplies, the server farm cooling can be more proficient and the expense of activity can be decreased. In this work, we dissect the power upward and dependability loss of …
Published in Journal of Power Electronics and Power Systems · Vol. 12, Issue 1, 2022 · pp. 36–43 Read article
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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell
Abstract: VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 73–77 Read article
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Sinusoidal Pulse Width Modulation Switching Technique based Single Phase Inverter
Abstract: This paper discusses about the inverter which transfers power from DC source to AC load side. Inverters are usually used in motor drive, static var compensators, uninterruptible power supplies (ups), etc. Pulse Width Modulation (PWM) technique is used because the total harmonics distortion is low as compared with other techniques. The switching scheme of sinusoidal PWM permits control of the frequency and the magnitude of the output. This switching scheme …
Published in Journal of Power Electronics and Power Systems · Vol. 9, Issue 1, 2019 · pp. 34–41 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Learning of Maximum Power Point Tracking Architecture with Various Algorithms for Photovoltaic Systems: A Review
Abstract: Currently, as the requirement on the Earth for ever more electricity grows, so too accordingly must demands upon renewable energy. These days, with the growth of renewable energy on all fronts, countries everywhere watch its development. Since demand for power generation goes up again, fossil fuels become less and less available, and expense is not coming down. When there is a rapidly changing irradiance, temperature, or partial shading, the output …
Published in Journal of Power Electronics and Power Systems · Vol. 16, Issue 2, 2026 · pp. 14–22 Read article
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Buck-Boost Chopper Control of Induction Motor Drive using Slip Power Recovery Scheme and LC Filter
Abstract: Industrial drive applications require rugged, low maintenance and simple constructed motors which are the features of induction motor. Speed control of SRIM can be accomplish by using either of the control technique i.e. rotor resistance control, inverter control & chopper control. This paper presents the improvements in the performance of SRIM drive offered by slip power recovery scheme using buck-boost chopper control technique with LC filter. The simulation model of …
Published in Trends in Electrical Engineering · Vol. 12, Issue 3, 2022 · pp. 42–59 Read article
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Analysis of LSDCCFF at 0.09 µm Technology
Abstract: The traditional low swing differential conditional capture flip-flop (LSDCCFF) for LC resonant clock distribution network has wide range of applications but has poor power consumption. These characteristics can be improved by using the modified LSDCCFF. This paper presents the design of modified LSDCCFF with less delay and low operating power. The implementation of the circuit is done using LSDCCFF. By using voltage scaling technique, the average power consumption can be …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 2, 2014 · pp. 32–39 Read article
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Voltage Sag Mitigation Using DVR and Ultra Capacitor
Abstract: Due to the rising integration of renewable energy sources into the power system, power quality issues have recently become more significant. Voltage sags and swells are among the biggest issues with a power system, and a lot of research has been done to try to solve these issues. Equipment for power conditioning can enhance the quality of the power. Dynamic voltage restorers (DVR) are used to shield sensitive loads from …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 3, 2022 · pp. 21–31 Read article
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Thermal Effects in High-Power Laser Systems: Modeling and Mitigation
Abstract: High-power laser systems are increasingly employed in industrial manufacturing, defense, medical procedures, and scientific research due to their ability to deliver high energy density with excellent spatial coherence. However, the performance and reliability of these systems are significantly influenced by thermal effects arising from optical absorption, non-radiative recombination, and inefficient heat dissipation within laser gain media and optical components. These thermal phenomena lead to adverse effects such as thermal lensing, …
Published in International Journal of Manufacturing and Production Engineering · Vol. 3, Issue 2, 2025 · pp. 9–13 Read article
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Modelling and Electrical Characterization of Single Electron Transistor
Abstract: A nano-electronic device with low power consumption, high performance, and quantum effects is the single electron transistor (SET). It's used in charge sensor applications, infrared radiation detectors, and spectroscopy. However, it faces limitations in lithography, co-tunneling effect, low gain, high output impedance, and background charges. Therefore, prior simulation is needed to optimize SET's work function and understanding physics concepts. A master equation approach is used to propose a new model …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 3, 2024 · pp. 19–25 Read article
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Low Power Area Efficient 4×4 Vedic Multiplier using GDI half adders with Better Delay Performance
Abstract: In the field of VLSI, wireless communication and digital signal processing, low power and area efficient architectures are considered. Majority of such applications uses multiplication. The multiplication is done using repetitive addition and shift and add method. It consumes more area delay and power. Vedic multiplier is one of the efficient multiplier. It is designed using different Vedic techniques or sutras, which reduces the area, power consumption and provide better …
Published in Journal of Control & Instrumentation · Vol. 10, Issue 2, 2019 · pp. 28–39 Read article
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Transistor Full Adder: A Comparative Performance Analysis
Abstract: AbstractIn this work the static energy recovery full adder named 10T13A with reduced 10 transistors is implemented. The fan in and fan-out of gates is also reduced by reducing number of transistors. Calculation of 10T13A full adder various parameters has been at 45 nm technology and compared with MTCMOS technique based 10T13A Full Adder. The active power has been calculated at 45 nm technology using Cadence Virtuoso Tool. Simulation results …
Published in Recent Trends in Electronics Communication Systems · Vol. 5, Issue 3, 2018 · pp. 22–31 Read article
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Design and Research of Thermoelectric Energy Harvesting Methods for Instantaneous Use
Abstract: In today’s consumer-oriented market, researchers are attempting to harness energy from ambient sources for sustainable energy generation leading to reduction of dependency on conventional energy sources. Energy harvesting methods offers enormous opportunities to derive energy from our natural surroundings to directly operate self-powered devices or storing it for later use. Generating energy from our nearby environment seems to be a promising solution to address the growing concerns of powering small …
Published in Trends in Machine design · Vol. 13, Issue 1, 2026 · pp. 18–33 Read article
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MAC Unit Implementation on FPGA
Abstract: Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 29–37 Read article
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QCA-based Implementation of Budget-friendly and Energy-Efficient Exclusive-OR/Exclusive-NOR Gates
Abstract: Quantum-dot cellular automata (QCA) is a novel nanoscale computational approach that proposes reduced dimensions, lower power consumption, increased speed, and deliberate design as a solution to the scaling challenge associated with CMOS technique. QCA is a nascent nanotechnology that utilizes the Coulomb repulsion principle. Quantum computing has emerged as a highly effective paradigm for the creation of energy-efficient hardware at the nanoscale. This article presents implementation of a very efficient …
Published in International Journal of Electro-Mechanics and Material Behaviour · Vol. 1, Issue 2, 2023 · pp. 1–6 Read article
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Design and Performance Trends of Low Power Sigma-Delta A/D Converters
Abstract: Analog-to-Digital Converters (ADCs) act as the bridge linking the real world and the digital world, i.e., they can covert the analog signal to the digital signal, and hence benefit to the storage, processing and transmission of the data. This paper presents a first of its kind study on the various Sigma-Delta (ΣΔ) ADC architectures proposed to achieve low power consumption and their performances have been compared with respect to the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 5–12 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article