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70 articles for “Adders”
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Implementation of 32 bit parallel adder using XILINX IPCORES A Case Study
Abstract: The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work compares the results obtained with the conventional Xilinx programming and the IP cores which are associated with it. VHDL programming style is used to describe the hardware and its functionality. Keywords: …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 2, 2020 · pp. 8–16 Read article
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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier
Abstract: Multipliers are the most important part in any arithmetic and logic unit, AbstractMultipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 1–10 Read article
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Performance Analysis of DG FinFET for Ultralow-power Subthreshold Applications
Abstract: Subthreshold operating region of transistor shows huge potential toward satisfying demand of ultralow power (ULP) consumption from handheld portable devices. However, operating device with such small subthreshold leakage current as a switching current gives huge penalty in their operating frequency. For subthreshold operating region key design goal is to boost the speed of the device. DG FinFET device shows excellent device characteristics in subthreshold operating region. In this paper, 1-bit …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 26–33 Read article
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit
Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article
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A Review for Power Optimization in MOS Devices using Different Logic Styles
Abstract: This paper presents power optimization in MOS devices by using different logic styles which is helpful for increasing high speed application. The simulation process can be done in different CMOS technologies and performance parameter of power is compared for different logic styles. Full adder and ripple carry adder are mostly used to define different logics to optimize the power. Constant logic style provides the low power and different logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 16–20 Read article
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
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Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits
Abstract: This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 · pp. 30–42 Read article
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Design of a Multipurpose Ternary Arithmetic Circuit Using CNTFET
Abstract: AbstractIn this paper, a multipurpose ternary arithmetic circuit is presented for ternary processors based on carbon nanotube field effect transistors (CNTFETs). Both addition and subtraction can be performed using same circuit’s configuration, which is the special feature of the proposed circuit. The combination of pseudo and complimentary logic structure are employed to blend the binary and ternary logic techniques. The propagation delay and power delay product are 139.5 pico second …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 13–24 Read article
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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32-bit Single Cycle MIPS RISC Processor
Abstract: In this report, I have written a Verilog HDL code for the MIPS 32-bit single-cycle RISC Processor and simulate the same. I have derived the result in four points first in terms of resource utilization, an RTL design view, TTL design view, and perform simulation on emulator using machine code. The topics I have cover the report are how to define instruction set for RISC architecture? Designing of various digital …
Published in Current Trends in Signal Processing · Vol. 12, Issue 1, 2022 · pp. 29–37 Read article
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Swing Restored Low Power and Area Efficient 8-bit Arithmetic Logic Unit Using Modified Gate Diffusion Input Technique
Abstract: AbstractThe arithmetic logic unit (ALU) is one of the most fundamental operational units in any processor. The ALU is the heart of any system or any processor and the core component of the central processing unit because mainly all the fundamental operations are performed by the help of ALU only. So, it can be defined as the combinational unit that is used to perform its logical and arithmetic units. The …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 19–29 Read article
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A Novel Architecture of Control System Processor Using Field Programmable Gate Array
Abstract: This paper presents a reconfigurable architecture of control system processor. The performance of the proposed architecture has been evaluated by taking different controllers and phase lead and phase lag networks. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 13–20 Read article