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34 articles for “field programmable gate array”
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THD Minimization of 27 Level Inverter using FPGA Control Strategy
Abstract: Normally single phase inverter gives only +230 V or –230 V. But multilevel inverter gives the variable output voltage in various levels and also the harmonics are reduced. If harmonics are produced, it affects the output of the load. Most of the industrial applications rely on Induction motors because of the reliable operation, low cost and simple construction. So the Multilevel inverter output is connected to the Induction motor. Here …
Published in Journal of Power Electronics and Power Systems · Vol. 3, Issue 3, 2013 · pp. 39–46 Read article
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Artificial Neural Network Implementation in FPGA using Multiplexer-based Weight Updating for Efficient Resource Utilization
Abstract: This paper presents a novel scheme for field-programmable gate array (FPGA) implementation of an artificial neural network (ANN). The proposed implementation is aimed at reducing resource requirement, without compromising on the speed so that a complex ANN architecture could be realized on a single chip at a lower cost. The weight updating process in different layers of the ANN has been carried using a simple MUX-based architecture. Backpropagation algorithm which …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 1–5 Read article
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FPGA Implementation of Variable Step Size Adaptive Filters for Signal De-noising
Abstract: This paper presents the design and implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. Four different adaptive filters (LMS, Sign-Data, Sign-Error and Sign-Sign) were designed using three different structures, viz., direct form, transposed and the proposed structure and their de-nosing performance was compared. Further, the filters were implemented on three different Field programmable gate arrays (FPGAs), viz., Spartan 6, Virtex 6 and Viretx 7 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 3, 2014 · pp. 7–19 Read article
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Vector Signal Transceiver (VST) in LabVIEW: A Review
Abstract: AbstractOver the past few decades, the increasingly popular architecture of RF systems with software has become increasingly popular. Almost every commercial automated RF system (COTS) today uses application software for communication via the bus interface with the device. As the complexity of radio frequency applications is increasing, engineers are constantly faced with the dilemma of increasing functionality without increasing testing time and, ultimately, to verify the cost. Although improvements in …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 1–5 Read article
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FPGA Implementation of LDPC Codes
Abstract: AbstractLow Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 21–28 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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Memristor based Material Implication Logic for Implementation of Basic logic Gates and Circuits
Abstract: A physical memristor was realized a few years back by Hewlett Packard labs. Instantly it became the topic of interest for many scientists and researchers. Memristor has joined resistor, capacitor and inductor in the list of basic two-terminal passive circuit elements. Field Programmable Gate Arrays (FPGAs) have become a major choice of technology for the implementation of various digital circuits because they offer various features such as quick time to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 17–22 Read article
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Optimized AES Implementation on Leon3
Abstract: This paper presents implementation of AES (Advanced Encryption Standard) on LEON3 which is a soft-core processor. We have used the AMBA (Advanced Microcontroller Bus Architecture) bus for interfacing our AES IP (Intellectual Property) core with Leon3 processor. AMBA bus is an in built open source bus which comes along with Leon3 processor. We have mainly analyzed parameters such as throughput, slice utilization and compared our model based with previous work. …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 30–33 Read article
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Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression
Abstract: Flexible and scalable motion estimation processor for the h.264 advanced video coding standard handling the processing requirements for high-definition video and suitable for Field-Programmable Gate Array (FPGA) implementation. The new motion estimation algorithm of kalman filter used to reduce the computational complexity. The eight custom instruction sets are used in the motion estimation. All processor instances are remaining binary compatible so recompilation process is not required. The motion estimation algorithm …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 1–5 Read article
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An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator
Abstract: This paper aims at designing a Field programmable gate array (FPGA)-based proportional, integral derivative (PID) controller in a servo-actuated control system. In the conventional method of implementing control systems in FPGA, there is no interaction between the controller and the system except for the final stage of implementing control system in the hardware. The proposed methods provide approaches for analyzing the performance of the controller and system in MATLAB simulink …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 1–6 Read article
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation
Abstract: Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 55–61 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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A Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB
Abstract: AbstractWe present “A Novel Conflict-Free Efficient Memory-Based Real Fast Fourier Transform (RFFT) using Urdhva Tiryagbhayam Butterfly”. In this paper different FFT lengths for address schemes are integrated that supports FFT processing which are used in diverse systems such as telecommunications. Address methods for various FFT lengths are coordinated in this paper to help FFT processing for different frameworks like broadcast communications. The memory bank and address can be produced by …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 3, 2019 · pp. 1–11 Read article
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Survey on Built in Self-Test (BIST) for FPGA Application
Abstract: The integration of Field- Programmable Gate Arrays (FPGAs) in various applications has surged in recent years due to their flexibility and reconfigurability. However, ensuring the reliability and functionality of these FPGAs is a critical concern. Built-in Self-Test (BIST) techniques have emerged as a promising solution to address this challenge by providing on-chip testing capabilities. This survey explores the landscape of BIST methodologies specifically tailored for FPGA applications. The study delves …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 3, 2023 · pp. 13–18 Read article