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42 articles for “Transistor Modeling”
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Intelligent Design Approaches in Microwave Engineering Using Machine Learning Techniques
Abstract: In microwave engineering, machine learning (ML) has become a potent technology allowing quicker design cycles, improved modelling accuracy, and automatic optimisation of complicated systems. Recent developments in the use of ML methods to microwave components and systems, including antennas, filters, and high-frequency circuits, are summarised in this study. In the framework of electromagnetic simulation, surrogate modelling, and parameter extraction, supervised and unsupervised learning algorithms are addressed. Moreover, the study looked …
Published in Journal of Microwave Engineering and Technologies · Vol. 12, Issue 2, 2025 · pp. 31–38 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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Designing of GaAs Based Resonant Tunneling Diode and Nano Scale Applications with Considering NEGF
Abstract: Present situation of eletronic area in the world required small devices as well as low power dissipation and ultra high speed application. At this moment the presence of resonant tunneling diode can over come this type of problem and take a big role in nanoscale digital and analog applications.In this researh article is to demonestrated effect of asymmetric barrier with respect to symmetric barrier and digital inverter and THz analog …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 1–18 Read article
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Unified Mathematical Framework for Semiconductor Devices, Junction Dynamics, and Circuit Analysis
Abstract: Semiconductor devices form the fundamental building blocks of modern electronic and integrated circuit systems, where their electrical behavior is governed by coupled carrier transport, electrostatic, and circuit-level phenomena. This work presents a unified mathematical framework for modeling semiconductor devices, junction dynamics, and their interaction with electronic circuits. The formulation integrates fundamental semiconductor relations, carrier concentration, drift–diffusion transport, Poisson’s equation, continuity equations, PN-junction behavior, diode characteristics, bipolar junction transistor operation, and …
Published in Journal of Semiconductor Devices and Circuits · Vol. 13, Issue 2, 2026 · pp. 37–47 Read article
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STUDY of MEMRISTOR MODELS and ITS APPLICATIONS in LOGIC CIRCUITS
Abstract: One significant area of nanotechnology is nanoelectronics. And a recent development in nanoelectronics is the discovery of the memristor, a fundamental circuit element. A memristor is essentially a nonvolatile nanoscale programmable resistor whose resistance, or memristance to be precise, is changed by applying a voltage across or current through, the device. Memristor has the potential to replace transistors in the digital circuit of upcoming days. Research is in full swing …
Published in Journal of Microelectronics and Solid State Devices · Vol. 1, Issue 1, 2015 · pp. 26–31 Read article
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Emerging Paradigms in Parallel Computing: Trends and Innovations
Abstract: Parallel computing is at an inflection point with revolutionary new paradigms and technologies. The goal of this paper is to survey the recent trend in parallel computing from architecture, programming model and applications. Mahajan cites a litany of architectural developments such as heterogeneous computing systems with integrated graphics processing unit/central processing unit ; the emerging promise from quantum and neuromorphic architectures (please see later); advances in packing transistors using novel …
Published in Recent Trends in Parallel Computing · Vol. 12, Issue 1, 2025 · pp. 39–43 Read article
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Polypyrrole-Based Conductive Polymer-Gated Single Electron Transistor with Deep Neural Network Assistance for Biomedical Energy Harvesting and Charge Detection
Abstract: The increasing demand for intelligent biomedical monitoring systems has accelerated research into ultra-low-power sensing technologies capable of operating with high sensitivity and minimal energy consumption. Conductive polymers have attracted considerable attention for biomedical and nanoelectronic applications due to their tunable electrical properties, biocompatibility, and environmental stability. Among them, Polypyrrole (PPy) is a promising functional polymer that can enhance charge transport and electrostatic coupling in nanoscale devices. In this work, a …
Published in Journal of Polymer & Composites · Vol. 14, Issue 4, 2026 Read article
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Numerical Simulation and Parameter Analysis for Pentacene based Organic thin Film Transistor with HfO2 Gate Dielectric
Abstract: This paper explains 2D numerical simulation and Characterization of Electrical parameter of Pentacene (Organic semiconductor) based Organic thin film transistor (OTFT) devices with HfO2 as a gate dielectric and Electrical parameters including; Threshold Voltage (Vt), Mobility (µ),Ion/Ioff, and Transconductance (gm), Sub threshold slope (SS) are extracted. The numerical simulation includes model for defect density of state and field dependent mobility model.
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 2, 2019 · pp. 28–34 Read article
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Design and Performance of Semiconductor-Biosensor
Abstract: In this work, a high electron mobility transistor (HEMT) based biosensor is designed to detect the virus-protein. In this work, all the simulation-studies are carried out in the SILVACO-ATLAS physical simulator using the following models: Shockley Read Hall (SRH), band gap narrowing, Auger recombination, and Fermi Dirac statistics. Newton trap numerical solver is used in the device simulation. Conduction band engineering of the biosensor is studied. DC and RF properties …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 2, 2021 · pp. 1–13 Read article
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Characterization of Low Power-Low Jitter Digital PLL
Abstract: The architecture design is being done in transistor level and tool which supports transistor level design. Mentor Graphics Tool is used for transistor level design and its simulation design. There are few tools which support design simulation like HSpice, Spectre and PSpice. Also a foundry support is from Taiwan Semiconductor Manufacturing Corporation (TSMC) (i.e.) technology model files 180 nm from TSMC for simulation. This article presents design for 1.5 GHz …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 23–32 Read article
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Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation
Abstract: This paper presents a machine learning (ML) assisted framework for the multi-objective optimization of nanoscale bulk n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with a 10 nm physical gate length, high-k HfO₂ gate dielectric, and TiN metal gate. Technology computer-aided design (TCAD) simulations employing drift-diffusion transport, Shockley-Read-Hall recombination, Lombardi mobility degradation, and density- gradient quantum correction models are used to generate a parametric dataset of 2,400 device configurations spanning gate length (L), …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 10–19 Read article
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Analysis of DIBL Effect in MOSFET Working
Abstract: AbstractOne of the most widely used electronic devices, particularly in digital integrated circuits, is the metal insulator semiconductor (MIS) transistor. Most of the existing transistors used in fabrication of integrated chips are with junctions. The device scaling is growing the channel length between junctions in devices are scaling gone down to 10 nm. Drain Induced Barrier Lowering (DIBL) effect is prominent as the feature size of MOS device keep diminishing. …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 33–40 Read article
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Comparison between First and Second Stage of Clock Drivers Using 65 nm PTM
Abstract: The paper is composed of generally two parts. The first part basically deals with the designing of clock distribution network for a branch-2 tree, also a wire model for 1 mm wire and designing a clock distribution network using wires and inverter pairs (buffers) to distribute a clock to the loads. Keeping this in to account simulation is analyzed and evaluated the results. The second part is to designing a …
Published in Journal of Microcontroller Engineering and Applications · Vol. 3, Issue 1, 2016 · pp. 10–15 Read article
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CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.
Abstract: Analog computing techniques are gaining attention for machine learning (ML) applications due to their ability to reduce computational complexity. Continuous operations such as addition and subtraction offer a simpler and more efficient approach compared to probabilistic product decoding, which can be sensitive to noise and inconsistent measurements. This paper presents a simulated VLSI implementation of a broadcast edge connection, independent of the MOS component model, along with experimental results. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 8–17 Read article
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Induction Motor Speed Control Using SCADA
Abstract: Single-phase induction motors are widely used in home appliances and industrial control because of their low cost and rugged construction. Many industrial processes require variable speed drives for various applications. This project investigates the speed control performance of single-phase induction motor using microcontroller AVR ATmega8a. PWM technique has been employed in this inverter to supply the motor with AC voltage. The 4n25 opto-coupler serves the purpose of isolation between the …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 5, Issue 1, 2017 · pp. 15–19 Read article
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Enhancing the Efficiency of Subthreshold Nanoscale MOSFETs for IoT Applications.
Abstract: In the contemporary landscape of the Internet of Things (IoT), this study focuses on the design and optimization of underlap Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors (SOI MOSFETs) tailored for real-time IoT applications. Employing an optimal spacer size (approximately 0.8 times the gate length, or LG), the device exhibits, at an operational frequency of20 GHz, an intrinsic gain of about 25 dB in the low to moderate inversion region (VOD=VGS– VTH≤90 mV, …
Published in Journal of Nanoscience, NanoEngineering & Applications · Vol. 13, Issue 3, 2023 · pp. 1–7 Read article
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Digital PID Chip Design and FPGA Synthesis
Abstract: The industrial applications follows the control operations based on closed loop system due to their stability and controllable desired response. The proportional-integral-derivative (PID) controller is one the most adopted controller in dynamic control systems. In some industries, specific PID controllers are used for particular control. The PID control is used for early days staring form mechanical and pneumatic designs, and its implantation is based on analog circuits using transistors. There …
Published in Recent Trends in Parallel Computing · Vol. 5, Issue 2, 2018 · pp. 13–19 Read article
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Design and Implementation of Low Power and High Speed 10T SRAM with High SNM
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell utilizes a strong cross-coupled structure that combines a standard inverter with a stacked transistor and a Schmitt-trigger inverter with a double-length pull-up transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 40–65 Read article
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A Reliable Low Standby Power 6T SRAM Cell
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 33–59 Read article
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Hierarchical Methodology Approach to SOC Design: A Comprehensive Look
Abstract: The design scale of a chip has increased many folds in the last few years and shows a continuous exponential trend. This is made possible by the reduction in transistor size and an evolving process technology. As a result, it is possible to move to SoC technology (System on Chip-A single die consisting of multiple subsystems) rather than a traditional ASIC. This has obviously resulted in an increase in the …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 35–42 Read article