STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Nanoscience, NanoEngineering & Applications

Enhancing the Efficiency of Subthreshold Nanoscale MOSFETs for IoT Applications.

  1. Indra Vijay Singh

Abstract

In the contemporary landscape of the Internet of Things (IoT), this study focuses on the design and optimization of underlap Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors (SOI MOSFETs) tailored for real-time IoT applications. Employing an optimal spacer size (approximately 0.8 times the gate length, or LG), the device exhibits, at an operational frequency of20 GHz, an intrinsic gain of about 25 dB in the low to moderate inversion region (VOD=VGS– VTH≤90 mV, where VOD, VGS, and VTH are the overdrive, gate, and threshold voltages, respectively).The study provides an accurate small-signal model that takes extrinsic parasitic effects and non-quasi-static effects into account for the optimized device. The optimized underlap device exhibits transit time frequency fT and maximum frequency of oscillation fMAX, measuring approximately 108 and 130 GHz,respectively, along with a noise figure (NF) of around 2.8 dB. It also exhibits a unilateral power gain(ULG) of around 38 dB at 20 GHz (VOD=90 mV, drain-to-source current IDS=0.64 mA, and drain-to-source voltage VDS=1 V). Comparing with a limited set of measured data indicates that the simulated results align well, suggesting the potential utilization of underlap device technology in the design of critical components like low-noise amplifiers (LNAs) and mixers for GHz IoT applications. This research lays the groundwork for the development of sophisticated electronic elements specificallycrafted to meet the rigorous demands of the rapidly expanding Internet of Things. It enhances the performance of crucial signal processing components operating in the GHz range.

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