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1979 articles for “1.25Cr-0.5Mo.” (ranking capped at the first 2,000 matches — narrow the search to see the rest)
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Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics
Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article
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Novel 1,3,4-Thiadiazole Derivatives: Design, Synthesis, Characterization and Anticancer Evaluation – A Review
Abstract: Cancer remains one of the leading causes of mortality worldwide despite significant advances in diagnosis and treatment. The clinical usefulness of many anticancer drugs is often restricted by toxicity, poor selectivity, and the emergence of drug resistance. These limitations have encouraged the search for novel heterocyclic compounds with improved therapeutic efficacy and safety. Among these, the 1,3,4-thiadiazole scaffold has gained considerable attention because of its favorable physicochemical characteristics, metabolic stability, …
Published in Research & Reviews: A Journal of Drug Design & Discovery · Vol. 13, Issue 2, 2026 · pp. 42–49 Read article
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Performance Analysis of 1-Bit Full Adder using GDI and CMOS Logic
Abstract: The adder is one of the most essential part in math processor, multiplier, and in various scientific applications. Full adder plays important role in multiplier architecture. In this paper a 1-bit full adder using GDI and CMOS logic has been implemented and comparative analysis has been done. The less delay and low power consumption is achieved for this implementation. This paper presents comparison of number of transistors have been used …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 18–22 Read article
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Implementation of 16-Bit Qam Using Texas Instruments
Abstract: In this paper, an implementation of 16-bit QAM is performed where there is a high use of Digital Video Broadcasting Cable (DVB-C), as there is increase in the usage the bandwidth requirement for each user is mutually increasing. Due to this, there is spectral congestion caused and drastic improvements have been taken in the field of communications. QAM multilevel modulation can offer an attractive solution to current bandwidth restriction in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 2, 2015 · pp. 14–20 Read article
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Design and Implementation of Low Power Area Effective 2×4 Decoder for SARM Applications Using 16 nm Technology.
Abstract: This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper study to reduce power dissipation and delay time which are fourteen 14-transistor and fifteen 15-transistor decoders. Every situation requires the use of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 24–36 Read article
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Design And Validation of High Efficiency Of 10T Sram with High Recoverability Of Multi Node Soft Error
Abstract: Sensitive nodes' critical charge is decreasing, which increases the soft-error vulnerability of SRAM cells used in aerospace applications. A single event upset (SEU) occurs when a radiation particle hits a sensitive node in a typical 6T SRAM cell, flipping the data that has been stored in the cell. Consequently, a Soft-Error-Aware Read-Stability-Enhanced Low Power 10T (SARP10T) SRAM cell is suggested in this project to reduce SEUs. The quadro cell exhibits …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 2, 2024 · pp. 7–14 Read article
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Seismic Analysis of Ductile Detailed Reinforced Concrete Structure for SMRF with & without Shear Wall with reference to IS13920:1993(Old Code) & IS13920:2016(Revised Code).
Abstract: Abstract The occurrence of earthquake has increased recently causing severe damage to human life and property. Hence accurate seismic analysis of structure is needed to be carried out considering all the parameters of the building. There are two methods for seismic analysis one is static and the other is dynamic method i.e. Seismic Co-efficient method for static analysis and Response Spectrum method for dynamic analysis of the building. In this …
Published in Journal of Structural Engineering and Management · Vol. 5, Issue 2, 2018 · pp. 74–80 Read article
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Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology
Abstract: A low Off-Set high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18µm …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 21–27 Read article
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Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology
Abstract: This paper proposes a review on study and analysis of an efficient fast low power 1 Kb SRAM cell using 90 and 45 nm Microwind technology. In this paper we have proposed the tentative improvement in performance parameters of SRAM cell like power dissipation, read or write speed, stability and signal to noise margin ration (SNM) using CMOS scaling.Keywords: SRAM, CMOS scaling, MicrowindCite this ArticlePathrikar A.K, Deshpande Rajkumar S. Design …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 1–3 Read article
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Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology
Abstract: Low noise amplifier (LNA) is terribly important block in designing broadband receivers for wireless broadband communications. Being the primary active element in receiver chain it creates larger demand for LNAs that are smaller, consume less power, and provide sufficient gain, low noise and high compact design. The projected LNA is extremely integrated with low noise figure having wide calibration range with improved RF power handling system and acquires less space …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 37–44 Read article
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A New High Speed Low Power 1 Bit Full Adder
Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
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Low-Voltage Low-Power Single Supply Rail-to-Rail High Resolution Comparator in 0.18 µm CMOS Technology
Abstract: This paper presents an absolute input rail-to-rail ultrahigh-resolution comparator for low-voltage low-power applications. To enhance the input range rail-to-rail, the proposed comparator utilizes dynamic configuration with a MOSFET-only clock booster to supply a boosted voltage for pre-amplifier stage. Cadence SPICE simulations of the proposed comparator in a 0.18 μm CMOS process confirm the rail-to-rail input range with a supply voltage of 1.2 V with a decision time less than 9 …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 87–91 Read article
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A Comparative Evaluation of a 13-story G+ Building with a Soft Storey, Using Pushover Analysis, with a Focus on the Impact of Different Placement of Shear Walls
Abstract: Asymmetrical structures with varying degrees of irregularity have proven to be a significant factor in causing collapses, damage to property, and injury during earthquakes. Despite extensive research on asymmetric buildings, there are currently no established guidelines for multi-story structures of this type. A soft storey, also known as a weak storey, is a level in a structure with insufficient rigidity or ductility to sustain earthquake-induced damage Pushover analysis has been …
Published in Recent Trends in Civil Engineering & Technology · Vol. 12, Issue 3, 2022 · pp. 1–9 Read article
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Performance Analysis of 160 Channel WDM System with EDFA Amplifier
Abstract: AbstractErbium Doped Fiber Amplifier (EDFA) amplifiers are popularly used in wavelength division multiplexing (WDM) system to compensate attenuation and dispersion. The performance of EDFA depends on various parameters such as, EDFA length, Er+3 doping concentration, active fiber length, pump power, pumping wavelength etc. This paper analyzed the performance of EDFA with counter pumping and co-pumping varying the EDFA length, pump power and Er+3 doping concentration and optimized the values for …
Published in Trends in Opto-electro & Optical Communication · Vol. 7, Issue 3, 2017 · pp. 25–34 Read article
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Effects of Variation of Active Region Radius on the Performance Characteristics of a Designed 1550 nm Al0.09Ga0.38In0.53As/InP MQW VCSEL
Abstract: AbstractIn this work, the performance characteristics of a designed Al0.09Ga0.38In0.53As/InP based 1550 nm top emitting multi quantum well (MQW) vertical cavity surface emitting laser (VCSEL) has been obtained. By evaluating the attained result of different parameters of selected MQW VCSEL the peak material gain is obtained as 1652.3 cm-1. For 6.1 mA of injection current and 5.65 µm of active region radius, the optical output power of 31.37 dBm and …
Published in Trends in Opto-electro & Optical Communication · Vol. 4, Issue 3, 2014 · pp. 8–13 Read article
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Optimized High Performance Characteristics of a Designed 1553 nm Wideband Travelling Wave Semiconductor Optical Amplifier
Abstract: AbstractIn this work, the performance characteristics of a designed 1553 nm Wideband Travelling Wave Semiconductor Optical Amplifier are presented. A high performance of the designed wideband SOA is obtained and analyzed with the optimized values of injection current, optical confinement factor, input power and active length. A maximum gain of 30.16 dB and minimum noise figure of 4.48 dB is obtained for 200 mA injection current, 0.33 optical confinement factor …
Published in Trends in Opto-electro & Optical Communication · Vol. 4, Issue 3, 2014 · pp. 32–39 Read article
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Design and Performance Analysis of a 635 nm Ga0.5In0.5P/(Al0.7Ga0.3)0.5In0.5P Multiple Quantum Well Separate Confinement Heterostructure Red Laser Considering Thermal Limitations
Abstract: AbstractIn this work, the performance characteristics of a GaInP - based 635 nm multiple quantum well (MQW) separate confinement heterostructure (SCH) Red laser has been obtained through computations. The material gain of Ga0.5In0.5P/(Al0.5Ga0.5)0.5In0.5P MQW edge emitting laser (EEL) has been theoretically obtained. The peak material gain obtained from the analysis has been used for analyzing the performance of the designed double-heterostructure laser. A maximum output power of 71.18 mW and …
Published in Trends in Opto-electro & Optical Communication · Vol. 3, Issue 1, 2013 · pp. 11–17 Read article
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Design of Folded Cascode Amplifier for SCL 180 nm Technology Node for Low Power Applications
Abstract: In this paper, a design and simulations of a Folded Cascode Amplifier at an SCL 180 nm Technology has been done and the different way to implement the design for a given specification has also been clearly demonstrated. The given design also clearly indicates the way to improve the various design parameters for a given specification of a circuit at this node. The way to reduce the power dissipation of …
Published in Journal Of Network security · Vol. 8, Issue 1, 2020 · pp. 22–31 Read article
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Graphical Representation and Interpretation of Data of Height/Weight of a Sample of 100 Humans in Relation to their Age and Sex
Abstract: AbstractThis paper presents recommendations for the analysis and presentation of height and weight data from surveillance or surveys involving age and sex in 100 human samples of variable ages. These recommendations are only for the analysis of data collected on a cross-sectional basis. The basic indices recommended are height for age and weight for height, each considered either in terms of centiles or in a cross-classification scheme using standard deviation …
Published in Research and Reviews : Journal of Computational Biology · Vol. 9, Issue 1, 2020 · pp. 40–51 Read article
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Arnold Chiari Type 1 Malformation: A Case Report
Abstract: Arnold Chiari malformation is neurological disorder in which there is down ward displacement of cerebellar tonsil through the foramen magnum. We are reporting a case of a 35-year-old woman with Arnold Chiari malformation Type - 1. Our patient presented with the history of headache for 1 month, pain right upper limb for 15 days. Pre-operative MRI was done to confirm the diagnosis. Patient was operated & discharged in 8 days. …
Published in Research and Reviews : Journal of Surgery · Vol. 3, Issue 1, 2014 · pp. 11–13 Read article