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193 articles for “A transistor”
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Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications
Abstract: In this paper, two designs of flash analog to digital converters (ADCs) based on threshold inverter quantization (TIQ) technique are presented. The parallel threshold inverter quantization (PTIQ) flash ADC exploits the advantage of reduction in capacitance and power consumption if the transistors are placed in parallel. Another design called low voltage tunable body bias (LVTBB) PTIQ ADC operates at near threshold voltage level to minimize the power consumption. The PTIQ …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 71–87 Read article
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Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology
Abstract: A low Off-Set high-speed two-stage dynamic comparator is presented in this paper. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 21–27 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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Simulation of Three Section Multilevel Inverter with Reduced Range of Switches
Abstract: Because of high generation development, the demand and excellent of electric strength ishigher than earlier than. Furthermore, due to the advancement of semiconductor, thespecification of electricity devices and strength conversion method turn out to be stricter. Oneof the energy converters that may remodel DC to AC is called inverter. An inverter is the intermedium to transmit the electricity to other electric device such as an uninterruptibleelectricity supply, servo motor, air-conditioner …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 1, 2020 · pp. 15–36 Read article
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Hierarchical Methodology Approach to SOC Design: A Comprehensive Look
Abstract: The design scale of a chip has increased many folds in the last few years and shows a continuous exponential trend. This is made possible by the reduction in transistor size and an evolving process technology. As a result, it is possible to move to SoC technology (System on Chip-A single die consisting of multiple subsystems) rather than a traditional ASIC. This has obviously resulted in an increase in the …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 35–42 Read article
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Quantum Behavior of Charge Carriers in a Symmetrical Double Gate MOSFET
Abstract: Our earlier work on modeling of single gate n-channel metal oxide semiconductor field effect transistor (MOSFET) has been extended to discuss the quantum behavior of charge carriers in symmetrical double gate (DG) MOSFET. The potential profile in the channel region of DG MOSFET has been obtained in parabolic approximation. The parabolic potential facilitates analytical expression for electric field. The appropriate Schrodinger’s equation has been solved to obtain wave functions in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 1, 2021 · pp. 17–28 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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Understanding of optical power in semiconductor based SOI Structure at the signal 1550 nm
Abstract: A silicon-on-insulator (SOI) structure consists of a single crystalline silicon layer separated from the bulk substrate by a thin insulator layer. The insulator in SOI wafers is usually always a thermal silicon oxide (SiO2) layer, with a silicon wafer as the substrate. The silicon sheet can be very thin (50 nm for fully depleted transistors) or tens of micrometres thick, depending on the application. Similarly, the thickness of buried oxide …
Published in Trends in Opto-electro & Optical Communication · Vol. 12, Issue 1, 2022 · pp. 19–23 Read article
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Low-power, High-speed, Full-swing Hybrid Full Adder
Abstract: Abstract: Nowadays VLSI design demands low area and low-power consumption. In this study, a low-power, high-speed, full-swing 1-bit hybrid full adder is proposed. The hybrid full adder is decomposed into three sub-modules. For each sub-module, designs are different. Module 1 and 2 are designed using pass transistor logic (PTL) and Module 3 uses transmission gates to produce carry signal. Then by proposed low-power, high-speed hybrid full adder circuits play a …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 7, Issue 3, 2019 · pp. 22–29 Read article
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Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit
Abstract: Scale down the size of devices introduce the effect of negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) in very-large-scale integration (VLSI) chip design and the major concern is to minimize these effects to a nominal value. In the paper, authors focus in minimization of NBTI effect and develop a noble degradation monitoring sensor circuit named SCHIMOS. A comparison is stated between an …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 8, Issue 1, 2020 · pp. 6–11 Read article
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A Short Review on Role of Nanotechnology in Daily Life
Abstract: Nanotechnology is latest technology of 21st century. It has impacts on each field of life. Below mentioned are various fields in which this technology is playing its positive role. Nanotechnology is predicted to change medicinal services by filling in as a novel technique for disease analysis as well as prevention, quality treatment, drug delivery plus gene therapy. In nanoelectronics, the look for a successor to Complementary metal–oxide–semiconductor (CMOS) innovation is …
Published in Research and Reviews : Journal of Computational Biology · Vol. 8, Issue 3, 2019 · pp. 24–33 Read article
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Sub-nano Regime DG-MOSFETs
Abstract: AbstractThe significance of device performance of Gallium Nitride based double gate metal-oxide- semiconductor field-effect-transistor has been executed. The simulations were done by Silvaco Atlas simulation software with focusing on non-equilibrium green function (NEGF). Multiple gate length (LG=9.1 nm) was observed to distinguish the transfer characteristics curve. The other concentration was observed for device ON-State Current (ION), OFF-State Current (IOFF), Drain Induced Barrier Lowering (DIBL), Sub Threshold Slope (SS) and Electric …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 1–6 Read article
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Unified Mathematical Framework for Semiconductor Devices, Junction Dynamics, and Circuit Analysis
Abstract: Semiconductor devices form the fundamental building blocks of modern electronic and integrated circuit systems, where their electrical behavior is governed by coupled carrier transport, electrostatic, and circuit-level phenomena. This work presents a unified mathematical framework for modeling semiconductor devices, junction dynamics, and their interaction with electronic circuits. The formulation integrates fundamental semiconductor relations, carrier concentration, drift–diffusion transport, Poisson’s equation, continuity equations, PN-junction behavior, diode characteristics, bipolar junction transistor operation, and …
Published in Journal of Semiconductor Devices and Circuits · Vol. 13, Issue 2, 2026 · pp. 37–47 Read article