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8 articles for “drain induced barrier lowering”
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A Two-Dimensional (2D) Analytical Model for Channel Potential and Threshold Voltage of Short Channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET
Abstract: In the present paper, an analytical model for the channel potential of short channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET has been presented using parabolic approximation method. Further, the threshold voltage of the device has been calculated using minimum mid channel potential and the result obtained has been compared with the threshold voltage of Triple Material double gate (TMDG) MOSFET in order to show the improvement in the threshold …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 13–25 Read article
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Analysis of DIBL Effect in MOSFET Working
Abstract: AbstractOne of the most widely used electronic devices, particularly in digital integrated circuits, is the metal insulator semiconductor (MIS) transistor. Most of the existing transistors used in fabrication of integrated chips are with junctions. The device scaling is growing the channel length between junctions in devices are scaling gone down to 10 nm. Drain Induced Barrier Lowering (DIBL) effect is prominent as the feature size of MOS device keep diminishing. …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 33–40 Read article
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Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation
Abstract: This paper presents a machine learning (ML) assisted framework for the multi-objective optimization of nanoscale bulk n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with a 10 nm physical gate length, high-k HfO₂ gate dielectric, and TiN metal gate. Technology computer-aided design (TCAD) simulations employing drift-diffusion transport, Shockley-Read-Hall recombination, Lombardi mobility degradation, and density- gradient quantum correction models are used to generate a parametric dataset of 2,400 device configurations spanning gate length (L), …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 10–19 Read article
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Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD
Abstract: In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness Tsi (20nm); gate oxide thickness Tox (3nm); buried oxide thickness Tbox (200nm) and gate length LG …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 7–17 Read article
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Reduction of Short Channel Effects with the Variation of Poly Doping and Source/Drain Doping
Abstract: In this paper, the concentration of poly-silicon doping and source/drain doping has been varied to obtain the approximation the OFF state leakage current for N channel MOSFET. A lightly doped NMOS has been designed using 45 nm technology in ATHENA and simulated in ATLAS of SILVACO TCAD tool. After simulation results, it has been observed that as the poly-silicon doping and source drain doping concentrations are decreased, there is a …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 3, 2017 · pp. 35–42 Read article
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GaN-based Double Gate MOSFET (DG-MOSFET)
Abstract: AbstractGaN is auspicious for high-power, high-temperature devices because of its large bandgap, and high saturation velocity compared with Si. Gallium nitride (GaN) based devices are expected to play an important role to develop the next-generation devices. The performance of GaN-based double gate (DG) MOSFETs have been explored with gate length (Lg) 10.6 nm. The ON-current (ION) and OFF-current (IOFF) are found to be 8.11´10–3 and 6.38605´10–9A/µm respectively, respectively with an …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 24–28 Read article
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Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime
Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article
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Sub-nano Regime DG-MOSFETs
Abstract: AbstractThe significance of device performance of Gallium Nitride based double gate metal-oxide- semiconductor field-effect-transistor has been executed. The simulations were done by Silvaco Atlas simulation software with focusing on non-equilibrium green function (NEGF). Multiple gate length (LG=9.1 nm) was observed to distinguish the transfer characteristics curve. The other concentration was observed for device ON-State Current (ION), OFF-State Current (IOFF), Drain Induced Barrier Lowering (DIBL), Sub Threshold Slope (SS) and Electric …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 1–6 Read article