Search
13 articles for “Xilinx”
-
VLSI Based Traffic Light Controller
Abstract: This study details the development and realization of an advanced traffic light control system utilizing VHDL (Very High-Speed Integrated Circuit Hardware Description Language) in conjunction with FPGA (Field Programmable Gate Array) technology. The system is designed to regulate a four-way intersection, with one primary high-traffic road intersecting with a less congested side road. To enhance traffic efficiency and minimize idle times, the model incorporates intelligent features such as a vehicle …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 2, 2025 · pp. 40–47 Read article
-
Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article
-
Design of a Verilog HDL-Based Advanced Intelligent Automatic Railway Gate Control System
Abstract: Human mistake, sluggish reaction times, and manual gate operation are common causes of railway level crossing accidents. This project suggests an Intelligent Automatic Railway Gate Controller made with Verilog HDL and simulated in Xilinx Vivado to lessen these mishaps. With the goal of improving safety at unmanned railway crossings, the system is intended to offer a dependable and entirely automated solution. Without human interaction, the railway gate is automatically controlled …
Published in International Journal of Electronics Automation · Vol. 4, Issue 1, 2026 Read article
-
Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation
Abstract: This paper introduces a novel and enhanced Gabor filter design aimed at addressing the demands of image processing applications using the Verilog Hardware Description Language (HDL). Specifically, it leverages the Reconstruct Gabor filter technique to elevate the performance and quality of standard image outputs. The primary objective of this research endeavor is to simplify the study, conduct an in-depth analysis, and substantially enhance the design's efficiency, all while ensuring the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 40–46 Read article
-
Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
-
Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
-
Design and Implementation of Low Latency 16-bit Full Adder
Abstract: In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing and systems play a vital role in the analysis and computation of data representation. Electronic systems have gradually become faster and smaller scale. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 21–31 Read article
-
Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
-
Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article
-
Novel approaches to the Design and Optimization of Universal Shift Register with Reversible logic
Abstract: Reversible logic is gaining importance in new multi-disciplinary fields, such as quantum computing, low-power computing, and even nanotechnology. The study of reversible gates has quickly evolved as a distinctive area of research as a result of the new developments aimed at fully utilizing resources and performing operations without any loss of information. With chip integration, these USRs, or Universal Shift Registers, have now become fundamental sequential components needed in various …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 21–28 Read article
-
Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
-
Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
-
Performance Analysis of AES Encryption Using LFSR-Based Key Expansion in VLSI
Abstract: Secure data transmission has become increasingly important with the rapid growth of digital communication and embedded systems. Protecting sensitive information from unauthorized access requires reliable cryptographic solutions. Among the available techniques, the Advanced Encryption Standard (AES) is widely recognized for its strong security and efficient implementation in both hardware and software environments. In this work, the design and performance evaluation of an AES-based crypto processor with LFSR-driven key expansion is …
Published in Recent Trends in Electronics Communication Systems · Vol. 13, Issue 1, 2026 Read article