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5 articles for “WSNM”
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Characterization of a Single-Ended Schmitt-Trigger based 9T SRAM Cell
Abstract: Data stability is a prime concern in submicron regime. This work presents a single-ended Schmitt- trigger (ST) based 9T static random-access memory (SRAM) cell. Proposed design provides enhanced read stability as it uses ST based inverters. Low power dissipation is achieved by employing just a single bit line. Simulation is carried out on gpdk 180nm CMOS technology on Cadence. Proposed design offers 1.36x improvement in read static noise margin (RSNM) …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 26–31 Read article
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Design of 10T SRAM Cell for Low Power and High Speed Applications
Abstract: AbstractThis paper presents techniques for designing a low-power and higher read speed Static Random Access Memory (SRAM) cell. The cell achieves low power dissipation due to Virtual Ground (VGND) scheme and provides higher read performance due to Forward Body Biasing (FBB). Design metrics of the proposed SRAM cell was studied and compared with that of CON 6T, CON D10T, TG 8T, 9T, and ST-10T SRAM cells. It was observed that …
Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 16–27 Read article
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Stability Analysis in SRAM Cell for Deep Submicron Design
Abstract: AbstractMemory is an integral part of present day battery operated and hand held electronic gadgets. As the size of devices shrinks so does the size of memory used in these devices also, this increases the demand for low power devices. Leakage current is one of the prominent factors that contribute to significant portion of the total power dissipation; in fact at lower technologies it becomes comparable to switching component. Device …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 2, 2018 · pp. 1–6 Read article
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Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability
Abstract: In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memory (SRAM) cell. The proposed cell employs cross-point data aware write structure, and thus supports bit interleaving architecture to mitigate soft errors. The proposed cell does not suffer from read disturbance as bit line is completely isolated from bit storage node. Simulation is done on 180 nm CMOS technology on Cadence. Read static noise margin (RSNM) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 5–10 Read article
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Impact of Work Function Variations on Data Stability of FinFET based 6T SRAM Cell
Abstract: The performance of FinFET SRAM cell is severely affected due to metal gate work function variations (WFV) in FinFET device. In order to provide guidelines for SRAM cell optimization, it is essential to examine the data stability due to the contribution of each cell transistor from WFV point of view. In this work, we investigate the effect of VTH variations of each transistor of tri-gated FinFET 6T SRAM cell on …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 1–13 Read article