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42 articles for “Transistor Modeling”
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Graphene and 2D-Material-Based Transistors for Next-Generation Nanoelectronics: Device Modeling and Performance Analysis
Abstract: The continuous scaling of conventional silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) has created increasing challenges related to short-channel effects, leakage current, electrostatic control, power consumption, and variability. Two-dimensional (2D) materials have emerged as promising channel materials for future nanoelectronics devices because of their atomically thin thickness, strong electrostatic controllability, and van der Waals interfaces provide opportunities for aggressive device scaling. Graphene, transition-metal dichalcogenides (TMDs), black phosphorus, hexagonal boron nitride, and related …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Computer Modeling of Organic Thin Film Transistors (OTFTs) using Verilog-A
Abstract: AbstractOrganic electronics has drawn considerable attention of the researchers with organic thin film transistors (OTFTs) as key components for various applications. Compared to the silicon industry where public models are well defined and commonly used to provide designers with a relative good description of any process, organic devices are still lacking for their complete device models that can fully describe their electrical characteristics. Therefore, compact model development for OTFTs is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 1–7 Read article
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SPICE Modeling of LDMOSFET Transistor
Abstract: AbstractHigh voltage integrated circuits, these days are the most viable alternatives to discrete circuits for various applications. The popular amongst them is the lateral double diffused MOS transistor (LDMOS). It is based on the lightly doped drain (LDD) concept. The constraint that occurred in modeling LDMOS is to minimize the on-resistance along with maintaining a high breakdown voltage. To achieve the objective, the help of RESURF (Reduced Surface Field) concept …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 42–57 Read article
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Numerical Simulation and Modeling of Graphene Field Effect Transistors for High Frequency Applications
Abstract: AbstractIn this paper numerical simulation of graphene field effect transistor (GFET) has been performed using finite element method by solving Poisson's equation, continuity equation and energy balance equation self consistently. Various performance characteristics including charge distribution, band gap energy, transfer and output characteristics, electrostatic potential distribution and transconductance have been extracted.Keywords: Graphene field effect transistor (GFET), energy balance equation, mobility, ambipolar, numerical simulationCite this ArticleAshish Jha, Dwivedi ADD. Numerical Simulation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 27–33 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design
Abstract: Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at …
Published in Journal of Nanoscience, NanoEngineering & Applications · Vol. 5, Issue 2, 2015 · pp. 20–31 Read article
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Modelling and Electrical Characterization of Single Electron Transistor
Abstract: A nano-electronic device with low power consumption, high performance, and quantum effects is the single electron transistor (SET). It's used in charge sensor applications, infrared radiation detectors, and spectroscopy. However, it faces limitations in lithography, co-tunneling effect, low gain, high output impedance, and background charges. Therefore, prior simulation is needed to optimize SET's work function and understanding physics concepts. A master equation approach is used to propose a new model …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 3, 2024 · pp. 19–25 Read article
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Modeling and Simulation of Pentacene based Organic Thin Film Transistors with Organic Gate Dielectrics
Abstract: AbstractTwo structures of pentacene organic thin film transistors (OTFT) with organic dielectrics, polymethyl methacrylate (PMMA) and polyvinyl alcohol (PVA) have been numerically simulated with TCAD ATLAS tool. Output and transfer characteristics were simulated and mobility, threshold voltage, sub threshold swing (SS) and current on/off ratio that play a part in the increment of conductivity of device were extracted. The authors show that the semiconductor-insulator interface actively affects the performance of …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 13–18 Read article
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Fabrication, Numerical Simulation and Compact Modeling of Ph-BTBT-C10 Organic Thin Film Transistor
Abstract: Flexible and cost-effective electronics have been necessitated by the advent of organic thin-film transistors (OTFTs). This study aims to study the performance of OTFT using a 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C10) organic semiconductor. The paper also explore accurate device modeling for technology optimization and circuit design that supports device improvement. This research includes device fabrication, numerical simulation using TCAD, compact modeling, and parameter extraction. By combining temperature-dependent bandgap narrowing with existing theories, this …
Published in Journal of Polymer & Composites · Vol. 12, Issue 5, 2024 · pp. 1–18 Read article
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Nonlinear Semiconductor Device Modeling using Neural Networks
Abstract: This paper describes the nonlinear semiconductor (transistor) of small and large signal modeling using a single neural network. Multilayer perceptron (MLP) with back-propagation (BP) learning is adopted in this work to model the drain current (ID) and the transconductance (gm) of the transistor. MLP modeling performance in terms of mean square error (MSE) and complexity of the network are illustrated briefly. Artificial neural network (ANN) model outcome for nonlinear function …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 1–6 Read article
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A Hybrid Cascaded Multilevel Inverter using Space Vector Pulse Width Modulation
Abstract: This paper proposes a topology of hybrid cascaded multilevel inverter consisting of two inverters namely main inverter and auxillary inverter. Main inverter consists of three-leg inverter with single DC source and auxillary inverter consists of three H-bridge two-leg inverter with separate DC sources for each H-bridge. Switches used in our proposed method are IGBT (insulated-gate bipolar transistor). The proposed model consists of 18 switches. The switches are controlled by space …
Published in Journal of Power Electronics and Power Systems · Vol. 5, Issue 1, 2015 · pp. 14–19 Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Design and Simulation of Ternary Gates Using Fin-FET
Abstract: In recent years, digital communication system has becomes more popular. But the on-chip interconnections have become a major problem as more and more modules are packed into a chip by reducing the gate size. As the gate size is reduced further the complexities in the circuit increases. Binary logic circuit dissipates a lot of energy, increase processing time, and causes coupling effect. In the Ternary logic system, there are three …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 4–18 Read article
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An overview of Nanocrystalline Hydrogenated Silicon Thin film Transistor
Abstract: This article elaborates and comprehends an overview on nc-Si:H TFT's, detailing and highlighting the topics like fabrication methodology, properties/stability, modelling, characterization techniques, challenges and futuristic scope/applications.With the growing demands in commercialization of Solar Cells (low-cost photo voltaic devices), Large Area Displays (like OLED’s), Thin film electronics (FPD applications), pixel switches, wearable/flexible electronics and so on, has prompted researchers to develop nc-Si:H TFT's (an alternative solution) which can out perform the …
Published in Nano Trends – A Journal of Nano Technology & Its Applications · Vol. 27, Issue 2, 2025 · pp. 1–23 Read article
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Quantum Behavior of Charge Carriers in a Symmetrical Double Gate MOSFET
Abstract: Our earlier work on modeling of single gate n-channel metal oxide semiconductor field effect transistor (MOSFET) has been extended to discuss the quantum behavior of charge carriers in symmetrical double gate (DG) MOSFET. The potential profile in the channel region of DG MOSFET has been obtained in parabolic approximation. The parabolic potential facilitates analytical expression for electric field. The appropriate Schrodinger’s equation has been solved to obtain wave functions in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 1, 2021 · pp. 17–28 Read article
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Physics of Semiconductors and Electronic Circuits
Abstract: This study talks about the basic ideas behind semiconductor physics and how important they are for making and running modern electronic circuits. It starts with a look at intrinsic and extrinsic semiconductors, going into how charge carriers move, energy band theory, and how doping affects how well the electricity flows. Next, the conversation turns to semiconductor devices like diodes, bipolar junction transistors (BJTs), and field-effect transistors (FETs). The focus is …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 9–17 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
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Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver
Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article
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Computational Modeling of Polymer Semiconductors for Electronic Applications
Abstract: Polymer semiconductors have become important materials in modern electronic applications because they combine semiconducting behavior with mechanical flexibility, low-cost processing, and tunable molecular structure. Their growing use in organic field-effect transistors, organic photovoltaics, organic light-emitting diodes, and flexible sensing devices has increased the need for accurate computational approaches that can predict material properties and device performance before experimental fabrication. This paper reviews the major computational modeling techniques used for polymer …
Published in Journal of Polymer & Composites · Vol. 14, Issue 3, 2026 · pp. 132–146 Read article