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5 articles for “SkyWater 130nm PDK”
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Implementation of a 4-Bit Synchronous Counter in SkyWater 130 nm CMOS Technology Using Open-Source EDA Tools
Abstract: As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 2, 2026 Read article
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In Silico Prediction of Multitarget Mechanism of Quinoline and Its Analogs on Phosphoinositide-3-Kinase Pathway Proteins
Abstract: Objective: Phosphoinositide 3-kinases (PI3Ks), the target of rapamycin (PI3K/Akt/mTOR, PAM), are a family of enzymes that play a role in the growth, proliferation, differentiation, motility, survival, and intracellular trafficking of cells, all of which are essential for healthy cellular function and are also connected to cancer. In this study, quinoline and its derivatives were employed to analyze its inhibition activity on the phosphoinositide-3-kinase pathway. Methods: In this work, eight phytocompounds …
Published in International Journal of Molecular Biotechnological Research · Vol. 1, Issue 1, 2023 · pp. 57–76 Read article
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RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools
Abstract: Exploring the RTL-to-GDS implementation of a high-speed on-chip 32:1 serializer, this study investigates the integration of open-source tools within VLSI design, emphasizing sustainable practices in the semiconductor industry while operating at the nanometer scale. Addressing methodologies for optimizing power consumption and chip area utilization, particularly focusing on efficient use of non-renewable resources. The study is set against the backdrop of advanced 7nm FinFET technology, critical for enabling efficient data transmission …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 1–10 Read article
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Noise-Resilient QPSK Modem for Reliable Communication for Green Communication
Abstract: The channel noise is the severely degraded the performance of communication system and that also limits the maximum data transmission rate. Hence, it is required to design a demodulator in a receiver which overcomes the effect of noise in the received signal, reconstructs un-corrupted information signal and improves data rate. In QPSK, noise effect the phase of the modulated signal and that causes error in the information signal. This study …
Published in Recent Trends in Electronics Communication Systems · Vol. 12, Issue 1, 2025 · pp. 36–46 Read article
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Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell
Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article