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32 articles for “Parallel Architectures”
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Parallel Privacy-Preserving Adaptive Federated Learning on GPU-Enabled Multi-Core Architectures
Abstract: The increasing deployment of parallel and distributed intelligent systems has intensified the need for privacy-preserving learning frameworks that can exploit multi-core and GPU-based architectures without centralizing sensitive data. This work proposes a parallel Adaptive Federated Learning (AFL) framework that integrates Differential Privacy and Secure Aggregation over heterogeneous multi-core and GPU platforms to enhance both data confidentiality and convergence efficiency. The framework dynamically adjusts client participation, learning rates, and aggregation weights …
Published in Recent Trends in Parallel Computing · Vol. 13, Issue 1, 2026 Read article
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Design and Optimization of Domain-Specific Languages for High-Performance Computing Applications
Abstract: The accelerating demand for computational power in scientific, engineering, and data-intensive domains has driven High-Performance Computing (HPC) systems toward unprecedented levels of parallelism and architectural complexity. Contemporary HPC platforms integrate multicore CPUs, many-core GPUs, accelerators, and deep memory hierarchies, creating significant challenges for software development and performance optimization. Traditional general-purpose programming languages and parallel programming frameworks provide low-level control over hardware resources but require extensive manual tuning, resulting in poor …
Published in Recent Trends in Parallel Computing · Vol. 13, Issue 1, 2026 Read article
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A Review of Blocking Side-Channel Threats in Parallel Cloud Systems
Abstract: Side-channel attacks (SCAs) pose a critical security threat to parallel computing systems, particularly in shared cloud environments where multi-tenancy and resource contention create exploitable vulnerabilities. This study presents a comprehensive review of SCAs in parallel architectures, analyzing attack vectors such as cache-based exploits (e.g., Prime + Probe, Flush + Reload), timing attacks, power analysis, and network-based covert channels. We examine real-world cases including Spectre and Meltdown vulnerabilities that exposed fundamental …
Published in Recent Trends in Parallel Computing · Vol. 12, Issue 2, 2025 · pp. 15–25 Read article
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Parallel and Concurrent Computing with Shell Commands: Exploring CPU Architecture, LAN Interconnection and Command Languages for Green Sustainability
Abstract: Parallel and concurrent computing are essential ways of thinking in the digital age, where the cost indexes are efficiency, speed and sustainability. By far performance relevance of each metaphor Contemporary computational environments covering everything from dumb terminals to distributed workstations and intelligent network systems such as the command-line interface (CLI) can never do well on its performance when throughput is needed most the era's fact that there is no hitting …
Published in Journal of Advances in Shell Programming · Vol. 12, Issue 3, 2025 Read article
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Comparative Analysis of Serial and Parallel Robot Mechanisms for Industrial Automation
Abstract: Serial and parallel manipulators represent two major mechanical architectures in industrial automation, each with distinct strengths and trade-offs. This study presents a detailed comparative analysis of serial-chain (open-kinematic) robots and parallel-kinematic manipulators (PKMs) with a focus on industrial automation tasks. It covers kinematics, static accuracy and stiffness, dynamics and actuation requirements, control and calibration burdens, workspace and singularity behaviour, and practical industrial considerations (cost, integration, safety, maintenance). Serial robots, exemplified …
Published in International Journal of Robotics and Automation in Mechanics · Vol. 3, Issue 2, 2025 · pp. 22–26 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Emerging Paradigms in Parallel Computing: Trends and Innovations
Abstract: Parallel computing is at an inflection point with revolutionary new paradigms and technologies. The goal of this paper is to survey the recent trend in parallel computing from architecture, programming model and applications. Mahajan cites a litany of architectural developments such as heterogeneous computing systems with integrated graphics processing unit/central processing unit ; the emerging promise from quantum and neuromorphic architectures (please see later); advances in packing transistors using novel …
Published in Recent Trends in Parallel Computing · Vol. 12, Issue 1, 2025 · pp. 39–43 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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MAC Unit Implementation on FPGA
Abstract: Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 29–37 Read article
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The Significance and Applications of Parallel Computing in the Modern Era
Abstract: This article explores the advancements in parallel computing, focusing on its applications in various domains such as scientific simulations, big data analytics, artificial intelligence, and real-time processing. We discuss the architectural shifts from traditional single-core processors to multi-core and many-core systems, along with the role of graphics processing unit (GPU)-based computing and specialized hardware like tensor processing units (TPUs) and field programmable gate arrays (FPGAs). Furthermore, the article examines contemporary …
Published in Recent Trends in Parallel Computing · Vol. 12, Issue 1, 2025 · pp. 24–38 Read article
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Automated Machine Learning System for Model Selection and Hyperparameter Optimization
Abstract: The proliferation of machine learning applications in various scientific and industrial domains has given rise to an urgent need for developing principled, automated techniques for optimal architecture selection and hyperparameter tuning for machine learning models without human expert intervention. In this paper, we introduce the Automated Machine Learning System for Model selection and hyperparameter Optimization (AMLSMO)—a state-of-the-art, all-encompassing AutoML system that combines the power of meta-learning-based warm-starting, Bayesian Optimization with …
Published in Recent Trends in Mathematics · Vol. 3, Issue 2, 2026 · pp. 15–23 Read article
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Hybrid Electric Vehicle: An Overview of Technology
Abstract: This article examines and explains the many HEV architectures and operating concepts, including as series hybrids, parallel hybrids, and series-parallel hybrids. The function of regenerative braking in hybrid electric vehicles (HEVs) is also covered; it allows energy to be recovered during braking and deceleration, improving total energy efficiency. The article also looks at key issues including battery technology, energy management plans, and powertrain integration that need to be considered while …
Published in International Journal of Electrical Power and Machine Systems · Vol. 1, Issue 1, 2023 · pp. 8–15 Read article
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Accelerating Unsupervised Feature Learning: Parallelized Training of Denoising Autoencoders
Abstract: Unsupervised representation learning has become a cornerstone of contemporary machine learning, enabling algorithms to extract informative features from un-labelled, high-dimensional data. This work investigates the efficacy of stacked denoising autoencoders (SDAEs) trained via parallelized stochastic gradient descent (SGD) as a scalable approach to feature extraction. By strategically leveraging multi-threaded computation, our study systematically examines the trade-offs between increased parallelism, training efficiency, and the preservation of model accuracy. Experiments on the …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 12, Issue 3, 2025 · pp. 56–64 Read article
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Footstep Power Generation Using Piezoelectric Materials: A Renewable Approach for Smart Infrastructure
Abstract: The rapid depletion of fossil fuels and the increasing global demand for sustainable energy have necessitated the development of decentralized energy harvesting systems. This paper presents a comprehensive study on footstep-based power generation using piezoelectric materials as a viable renewable energy solution for smart infrastructure. The proposed system converts mechanical energy generated from human locomotion into electrical energy using optimized piezoelectric transducer arrays integrated beneath floor tiles. The study covers …
Published in Trends in Electrical Engineering · Vol. 16, Issue 1, 2025 Read article
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Challenges in Parallel Computing for Big Data Analytics
Abstract: The integration of parallel computing into the realm of big data analytics promises accelerated processing speeds and enhanced scalability, but it is not without its formidable challenges. This study explores the multifaceted hurdles faced in the pursuit of efficient parallel processing for large-scale data analytics. The intricate task of distributing and partitioning massive datasets across multiple processing units demands adept strategies to ensure equitable workloads. Load balancing emerges as a …
Published in Recent Trends in Parallel Computing · Vol. 11, Issue 1, 2024 · pp. 1–6 Read article
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Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Abstract: The three operands binary adder is a basic function used in the creation of modular arithmetic in various algorithms, such as the pseudorandom bit generator and cryptography. The CS3A carry save adder is commonly used to perform this operation. Nevertheless, the operation's outcome delayed the transmission of O(n) because of the ripple carry step. A dual-optoic adder for parallel prefix computation, such as the Han-Carlson method, can be used to …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 14–22 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
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Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics
Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article
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Parallel Greedy Approach for Phylogenetic Tree Construction in the Context of Marine Species
Abstract: The rebuilding of phylogenetic trees for marine species shows major computing problems because of the massive genomic data and the huge biodiversity inherent in ocean ecosystems. Traditional phylogenetic methods are accurate but become more expensive when they are processing with thousands of marine taxa parallelly. This article shows a critical analysis of parallel greedy algorithms as an adaptable solution for large-scale marine phylogenetics. It examines the main principles of greedy …
Published in International Journal of Algorithms Design and Analysis Review · Vol. 4, Issue 1, 2026 · pp. 33–45 Read article
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Parallelization of Metaheuristics for the Optimization of Permuted Perceptron Problem
Abstract: Parallel computing has found a mainstream backing in graphics processing units (GPUs).These resources have enormous processing capacity, are energy efficient, and are broadly available, unlike grids. Since the advent of CUDA (Compute Unified Device Architecture) developed by NVIDIA that permits GPU programming in C, C++ language, GPUs are now being used in a variety of fields, including scientific computing. This thesis focuses on the optimization of the solution of a …
Published in Journal of Operating Systems Development & Trends Read article