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8 articles for “NMOS”
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Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
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Implementation of STATIC-RANDOM-ACCESS-MEMORY-Based In-Memory Computing-architecture for improving Energy Efficiency
Abstract: The in-memory-computing architecture the improvement of big data and high-performance computing. In memory-computing (IMC) as reduces the latency and power consumption of data processing. Proposed research paper static random-access memory-based IMC architecture. By completing internal write-back, NMOS transistors increase computational efficiency and eliminate the need to read the computational output right away. A 128×128 STATIC-RANDOM-ACCESS-MEMORY-IMC macro chip is designed using the 78-nm technology. The energy efficiency of 55.3TOPS/W with supply …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 25–35 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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A High Frequency and Power Efficient Memristor Emulator and Its Application
Abstract: This study presents a small, energy-efficient memristor emulator made for use at high frequencies. The proposed circuit has a simple design that only includes three n-type MOSFETs and a grounded capacitor. This means that there is no need for active components or DC biasing. This streamlined architecture not only makes things easier, but it also uses very little power, with dynamic and static power measured at 15.82 μW and 65.6 …
Published in International Journal of Electrical and Communication Engineering Technology · Vol. 3, Issue 2, 2025 · pp. 45–52 Read article
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Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation
Abstract: This paper presents a machine learning (ML) assisted framework for the multi-objective optimization of nanoscale bulk n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with a 10 nm physical gate length, high-k HfO₂ gate dielectric, and TiN metal gate. Technology computer-aided design (TCAD) simulations employing drift-diffusion transport, Shockley-Read-Hall recombination, Lombardi mobility degradation, and density- gradient quantum correction models are used to generate a parametric dataset of 2,400 device configurations spanning gate length (L), …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 10–19 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article