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15 articles for “IP cores”
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All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey
Abstract: An all-digital phase locked loop (ADPLL) plays a great role in decreasing the development time of an application-specified integrated circuit (ASIC) products and helps to meet the time-to market requirement of product, because an ADPLL can be used as an IP core, so it is easily reusable in any design. Now a days ADPLL is being widely used in various fields such as control systems and digital communication systems. This …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 12–17 Read article
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Design and Analysis of EV Controller using IPMSM Taking Core Loss into Account
Abstract: Now a days vehicles with electrical differentials are becoming more and more popular. The mechanical differentials are replaced by using two motors. In the electrical vehicle (EV) different types of electrical machines such as induction motor, permanent magnet synchronous motor etc. are used. The controller design for the different motors is a fascinating and challenging work to obtain desired performance properly. The interior-permanent magnet synchronous motor (IPMSM) has already been …
Published in Journal of Control & Instrumentation · Vol. 6, Issue 2, 2015 · pp. 1–8 Read article
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Modeling and Performance Analysis of Electrical Vehicle with SPWM Inverter-fed IPMSM Taking Core Loss into Account
Abstract: Because of the advantages of electrical differentials, people are becoming more interested in using them rather than using mechanical differentials. The mechanical differentials are replaced by using the two rear motors. In the electrical vehicle (EV) different types of electrical machines such as induction motor, permanent magnet synchronous motor etc. are used. The design of a controller is a challenging work, as the output of the motor has to match …
Published in Journal of Control & Instrumentation · Vol. 7, Issue 1, 2016 · pp. 7–16 Read article
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Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA
Abstract: Complex multiplication is an important operation frequently used in the digital signal processing. This paper shows the resource utilization for a complex multiplication on Spartan3E by using a 9 bit floating point numbers. The proposed method clearly shows that resource utilization for complex multiplication is less than the IP cores proposed by the Xilinx Company. More over this paper shows how the significant and the exponent of the floating point …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 9–14 Read article
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Power Estimation Approach for Artix 7 FPGA using Machine Learning Technique
Abstract: Abstract This paper presents the power estimation approach using a suitable machine learning technique. Artix7 FPGA has been chosen as the target FPGA (Field Programmable Gate Arrays) platform for understanding the methodology of power estimation. There are various approaches of power estimation for FPGAs that have been given in the literature viz. probabilistic, statistical, and LUT-based, etc. In the past few years, the demand for hand-handled devices like smartphones, tabs, …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 1, 2021 · pp. 1–5 Read article
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Speed Control of An Inverter Fed Three-Phase Induction Motor Using IP Controller Considering Core Loss and Stray Load Loss
Abstract: Consideration of core losses and stray load losses to design a controller of an inverter fed induction motor are affected to the flux and torque decoupling strategy adversely. As a consequence, the detuning of field-oriented control (FOC) is required. The detuning strategies have been developed in some literatures. But the implementation of detuning becomes difficult because of higher order expression. In general, the controlling and estimation of AC drives are …
Published in Trends in Electrical Engineering · Vol. 5, Issue 1, 2015 · pp. 28–35 Read article
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Implementation of 32 bit parallel adder using XILINX IPCORES A Case Study
Abstract: The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work compares the results obtained with the conventional Xilinx programming and the IP cores which are associated with it. VHDL programming style is used to describe the hardware and its functionality. Keywords: …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 2, 2020 · pp. 8–16 Read article
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Power Estimation Approach for Artix 7 FPGA using Machine Learning Technique
Abstract: This paper presents the power estimation approach using a suitable machine learning technique. Artix7 FPGA has been chosen as the target FPGA (Field Programmable Gate Arrays) platform for understanding the methodology of power estimation. There are various approaches of power estimation for FPGAs that have been given in the literature viz. probabilistic, statistical, and LUT- based, etc. In the past few years, the demand for hand-handled devices like smartphones, tabs, …
Published in Research & Reviews: A Journal of Embedded System & Applications Read article
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Implementation of Weighted Round Robin Algorithm in Shared Bus Architectures
Abstract: AbstractThe application domain of System-On-Chips (SoC) includes mobile devices, end terminals, multimedia terminals, automotive, set-top-boxes, games, processors etc. The SoC design paradigm relies heavily on reuse of intellectual property cores, enabling designers to focus on functionality and performance of the overall system. This is possible if IP cores are equipped with highly optimized interface for plug and play insertion into communication architecture. To this purpose the virtual Socket Interface Alliance …
Published in Journal of Electronic Design Technology · Vol. 8, Issue 2, 2017 · pp. 34–40 Read article
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The Emerging Technologies in the Field of Semiconductors Along with the Use of the System on Chip
Abstract: An entire electronic or computer system can be combined onto a single platform using a system on chip, which is effectively an integrated circuit. The primary objectives underlying the development of this system on chip are to decrease energy waste, cut costs, and decrease the area occupied by massive systems. Students can understand and experience many methods utilised at each level of the design hierarchy using this strategy. The expansion …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 8–15 Read article
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Modeling, Analysis and LQR Control of an EV Differential using IPMSM
Abstract: Recently, the mechanical differential (MD) of vehicle has been replaced by electronic differential (ED) by means of electric motor. Electronic differential ensures dynamic and robust control of the vehicle behavior. The ED has been designed for an electrical vehicle (EV) based on IPMSM due to its some inherent advantageous features. The design of speed controller of an IPMSM mainly depends on its mathematical model. The mathematical model based speed controller …
Published in Journal of Control & Instrumentation · Vol. 7, Issue 2, 2016 · pp. 23–34 Read article
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Optimized AES Implementation on Leon3
Abstract: This paper presents implementation of AES (Advanced Encryption Standard) on LEON3 which is a soft-core processor. We have used the AMBA (Advanced Microcontroller Bus Architecture) bus for interfacing our AES IP (Intellectual Property) core with Leon3 processor. AMBA bus is an in built open source bus which comes along with Leon3 processor. We have mainly analyzed parameters such as throughput, slice utilization and compared our model based with previous work. …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 30–33 Read article
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IP Transcendence: Unifying IPv6 Over IPv4 Network
Abstract: Dynamic routing also called adaptive routing like traditional glass optical fiber, POF uses a polymethyl methacrylate (PMMA) core with a fluorinated polymer cladding, resulting in a larger core diameter that simplifies alignment and splicing. POF's adaptability is one of its main benefits. Because of their fragility and stiffness, ordinary glass fibers would not be practicable in certain situations where POF can be put. POF is a great option for intricate …
Published in International Journal of Electrical Power and Machine Systems · Vol. 2, Issue 1, 2024 · pp. 36–42 Read article
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Design of a 4X4 Network-on-Chip Crossbar Router in a System-on-Chip
Abstract: With the number of IPs increasing in an SoC, there is a need for achieving high bandwidth, low latency, scalable multi-core intercommunication and solve the shortcoming of buses. Network-on-chip is a technology which is a solution for such problems. Network-on-chip solves the problem by implementing a communication network of switches, routers and resources. This paper proposes a design for communication among subsystems between intellectual property cores in an SoC design. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 3, 2015 · pp. 28–35 Read article
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Study and Design of Reconfigurable Processor Peripherals using Xilinx Tools
Abstract: AbstractXilinx Platform Studio used in this paper to create a reconfigurable processor system. The Xilinx Embedded Development Kit (EDK) software allows mapping processor of a Microblaze plus several on-chip peripheral bus (OPB) peripherals. The EDK bridges the gap between Hardware (HW) and Software (SW), flows by providing a single HW/SW design environment. Xilinx ISE is to create a top-level design hierarchy. It extends a fully software architecture by generating and …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 17–23 Read article