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45 articles for “Arithmetic operation”
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Design of Three-Stage Pipelined Floating Point Arithmetic Operators
Abstract: Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM and multiplexer …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 9–22 Read article
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A Novel Binary Arithmetic Computational Method
Abstract: The proposed algorithm for arithmetic operations presents an innovative and intriguing approach, primarily centered around the use of counters and the manipulation of '1's in binary representations. This algorithm promises to introduce significant advancements in computational efficiency and accuracy, making it a potential game-changer in the field of arithmetic calculations. At the core of this method lies the reliance on the number of '1's in each location within a binary …
Published in Research & Reviews: Discrete Mathematical Structures · Vol. 10, Issue 1, 2023 · pp. 21–25 Read article
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Swing Restored Low Power and Area Efficient 8-bit Arithmetic Logic Unit Using Modified Gate Diffusion Input Technique
Abstract: AbstractThe arithmetic logic unit (ALU) is one of the most fundamental operational units in any processor. The ALU is the heart of any system or any processor and the core component of the central processing unit because mainly all the fundamental operations are performed by the help of ALU only. So, it can be defined as the combinational unit that is used to perform its logical and arithmetic units. The …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 19–29 Read article
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Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Abstract: The three operands binary adder is a basic function used in the creation of modular arithmetic in various algorithms, such as the pseudorandom bit generator and cryptography. The CS3A carry save adder is commonly used to perform this operation. Nevertheless, the operation's outcome delayed the transmission of O(n) because of the ripple carry step. A dual-optoic adder for parallel prefix computation, such as the Han-Carlson method, can be used to …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 14–22 Read article
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A Survey: E-Ball Technology and its Features
Abstract: AbstractThe E-Ball is a sphere-shaped computer concept which is the smallest design among all the laptops and desktops have ever prepared. It is very small, it is having only 6-inch diameter ball. The word “computer” comes from the word “compute" that is to calculate or operate. People usually consider a computer to be a calculating device that can perform arithmetic operations at high rapidity. It is a new concept of …
Published in Journal of Open Source Developments · Vol. 4, Issue 2, 2017 · pp. 10–12 Read article
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Projectivity of Universal Algebras
Abstract: The basic relations between universal algebras are homomorphisms and their special cases – monomorphisms, epimorphisms, and isomorphisms (cf., for example, (Kurosh, 1963; Cohn, 1965)). In this paper, we introduce and study a novel relation between universal algebras, which is called projectivity and allows obtaining properties of universal algebras from properties of those universal algebras to which they are weakly or finally projective. The key property of projectivity relations is that …
Published in Research & Reviews: Discrete Mathematical Structures · Vol. 9, Issue 1, 2022 · pp. 6–20 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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An Efficient Tree Structure 32-Bit Brent-Kung Adder for Reducing Time Delay and Memory Utilization
Abstract: AbstractBrent-Kung adder is such of the parallel prefix adders secondhand for speeding of the operation. Parallel prefix adders are the fast adders and dig the arithmetic operations at the expeditious rate. Most Industries are like TMSC, Texas, are used by parallel prefix adders seeing of their advantages compared to a variance adder. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a campaign for increasing the speed …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 29–35 Read article
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Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder
Abstract: Carry select adder is the high speed adder which is designed to speed up arithmetic operations and to reduce the computation time. Carry select adder is used to perform fast arithmetic functions in data processing processors. Low power consumption, reduced area, reduced delay and increased speed are the most important features of the modern electronic system design. In this proposed work, 8 transistor full adder (8T full adder) is used …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 25–29 Read article
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A Review on Comparison of Vedic Multipliers Using Various Types of Adder Topologies
Abstract: Abstract: This paper examines the displays of comparison of Vedic multipliers using various adders. In the design of most high-performance systems such as FIR filters, image processing, microprocessors multipliers are the integral components and multiplication is the important fundamental function in arithmetic operations. Multiplication is the most important job in signal processing apps for numerical operations. Since speed in the multiplication procedure is dependably a must, velocity increases can be …
Published in Journal of Operating Systems Development & Trends · Vol. 6, Issue 3, 2019 · pp. 1–8 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article
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4-Bit Magnitude Comparator Design using Different Logic Styles
Abstract: 4-Bit Magnitude Comparator using various logic styles is explained here. Comparison is one of the common arithmetic operations that is used to determine which number is greater, equal to, or less. Every device from OP-AMP to ALU needs to perform comparison operations. At designing level, comparator can be designed by using different logic styles. Here, comparison is done for simple 4-Bit combinational comparator and cascaded comparator which we have designed …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 16–22 Read article
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The Evolution and Impact of Numbers: From Ancient Tallies to Quantum Computing: Review Article on Numbers
Abstract: Numbers are among the most fundamental constructs in human civilization, serving as the backbone of mathematics, science, technology, and virtually every aspect of daily life. They represent not only quantities and measures but also relationships, structures, and patterns that underpin the fabric of human understanding. From the earliest tallies etched on bones by prehistoric humans to the sophisticated numerical systems embedded in today’s artificial intelligence and quantum computing, the evolution …
Published in Research & Reviews: Discrete Mathematical Structures · Vol. 12, Issue 3, 2025 · pp. 15–19 Read article
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An Automated Smart Contract Repair Framework for Reentrancy, Integer Overflow, and Denial- of-Service Vulnerabilities
Abstract: This paper introduces a novel static analysis framework designed to bridge a long-standing gap in Ethereum smart contract security: the disconnect between vulnerability detection and automated remediation. Although widely adopted tools such as Slither and Oyente are highly effective at identifying security weaknesses, they stop short of providing actionable fixes. As a result, developers manually patch vulnerabilities, a process that is not only time-consuming but also susceptible to human error …
Published in Journal of Computer Technology & Applications · Vol. 17, Issue 1, 2026 · pp. 31–41 Read article
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Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier
Abstract: Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high-speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16 …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 7–14 Read article
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Implementation of Carry Select Adder with Reduced Area Scheme
Abstract: Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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Implementation of Floating Point Multiplier Using Dadda Algorithm
Abstract: Floating point multiplication is very useful in all the computation applications like in arithmetic operation, DSP application etc. To achieve higher speed of the mantissa, multiplication is done using Dadda multiplier which works on the basis of Dadda algorithm. Through this architecture we gain high speed with a maximum frequency and also reduce the number of gates compared to existing multipliers; and through floating point format it is possible to …
Published in Journal of Multimedia Technology & Recent Advancements · Vol. 3, Issue 1, 2016 · pp. 16–22 Read article