Search
603 articles for “bit-banged PWM”
Nothing matched all of your words, so these match any of them.
-
Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics
Abstract: AbstractAdder is required for many processors designing like microprocessors, digital signal processors, image processing and various VLSI applications. The overall performance of system depends upon the adder circuits due to its presence mainly in critical paths of system. This paper presents half adder circuits using different combinational MOS logics. All the circuits were analyzed to find the most suitable circuit which consumes less power without costing the speed of the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 19–27 Read article
-
Design and Analysis of a 100 kWp Grid Connected PV Solar Plant at a Coastal Area of Bangladesh
Abstract: In Bangladesh, the usage of electricity is continuously increasing. Govt. is also trying to increase the electricity production by installing new power plants to meet the additional power demands. Most of the power plants are natural gas-based, coal-based or nuclear power-based. Considering the greenhouse effect; solar power plants could be one of the best solutions to meet the additional power demands as well as it has a lot of financial …
Published in Journal of Power Electronics and Power Systems · Vol. 11, Issue 3, 2021 · pp. 33–39 Read article
-
An Optimized 32 bit Carry Select Adder Using Modified BEC
Abstract: AbstractAdders play a major role in addition of numbers, multiplications and other advanced processors’ design. Among the conventional adder structures, carry select adder is known to be fastest adder. This adder circuit is used for the design of high speed processors. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. CSLA circuit for 8, 16, 32 bits is designed without multiplexer …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 27–32 Read article
-
An Efficient Tree Structure 32-Bit Brent-Kung Adder for Reducing Time Delay and Memory Utilization
Abstract: AbstractBrent-Kung adder is such of the parallel prefix adders secondhand for speeding of the operation. Parallel prefix adders are the fast adders and dig the arithmetic operations at the expeditious rate. Most Industries are like TMSC, Texas, are used by parallel prefix adders seeing of their advantages compared to a variance adder. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a campaign for increasing the speed …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 29–35 Read article
-
Developing Design Charts for Lateral Loads in High Seismic and High Wind Zone of Bangladesh According to BNBC 2020
Abstract: This study investigated seismic base shear and wind base shear for typical residential building of different story according to newly adopted BNBC 2020, which is a regional modification of ASCE 7-05. For the study we considered six building of different height and lateral load resisting system situated in high seismic and high wind zone, Chattogram, Bangladesh. For this reason, three-dimensional building model was prepared using ETABS V.18 with loading provisions …
Published in Journal of Structural Engineering and Management · Vol. 9, Issue 1, 2022 · pp. 34–43 Read article
-
A New High Speed Low Power 1 Bit Full Adder
Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
-
Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
-
Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder
Abstract: Carry select adder is the high speed adder which is designed to speed up arithmetic operations and to reduce the computation time. Carry select adder is used to perform fast arithmetic functions in data processing processors. Low power consumption, reduced area, reduced delay and increased speed are the most important features of the modern electronic system design. In this proposed work, 8 transistor full adder (8T full adder) is used …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 25–29 Read article
-
Design of 16-bit Pipelined RISC Processor
Abstract: This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 32–37 Read article
-
Design and Implementation of Low Power 8-bit Level Crossing ADC
Abstract: Implantable medical devices, electronic gadgets, wireless communication elements and many other such applications require low power electronic circuits. Analog to digital converters are essential part of most of such circuits. This paper presents a design of the level crossing analog to digital converter (LC-ADC) architecture. The proposed circuit and layout has been implemented in semi-conductor laboratory (SCL) 180 nm technology and its performance was evaluated using cadence virtuoso at supply …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 33–43 Read article
-
Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization
Abstract: Multipliers play important role in the digital VLSI design. Computational Speed, power consumption, and area are the major parameters on which the performance of the device depends. In digital design, there are different multiplication methods or algorithms. Each algorithm is having its own advantage and disadvantage. In this paper, implementation of five different types of 8-bit multipliers namely Array multiplier, Booth multiplier, Truncated multiplier, Pipelined multiplier, and Vedic multiplier has …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 22–34 Read article
-
PWM Technique based evaluation and performance analysis ofZVS Based Resonant Converter
Abstract: A Zero Voltage Switching (ZVS) based Resonant Converter (RC) has been simulated and the performanceis analyses in this paper. A ZVS based resonant converter working under load independent output voltage and no-load regulation is presented in the paper.Pulse width modulation (PWM) is a technology used to regulate outputvoltage. The major transitions of a full-bridge converter that achieves zero-voltage switching across the whole lineand load range by using a linked inductor …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 42–48 Read article
-
Analysis of Rainfall Variability in Sylhet Region of Bangladesh
Abstract: The variability and distributions of rainfall of a region is important and useful especially for agricultural activities. The study was conducted to establish the rainfall trends in Sylhet by analyzing available rainfall record for 35 years period of 1981 to 2015. Records of daily rainfall data for Sylhet region were obtained from the Bangladesh Meterological Department (BMD) for analysis. Rainfall data were categorized into monthly, annual, and seasonal basis. The …
Published in Journal of Water Resource Engineering and Management · Vol. 6, Issue 2, 2019 · pp. 1–10 Read article
-
Estimation of BOD of Banganga Nalla of Bhopal City Using Statistical Methods
Abstract: Water is a precious natural source without which life cannot be sustained. Surface water has been the main source of supply for all our purposes. It is also has been the most convenient sewer for industry and municipalities. Estimation of water quality parameters using statistical and other mathematical models are gaining importance because they give more rational basis for water quality planning. An attempt has been made in this paper …
Published in Journal of Water Resource Engineering and Management · Vol. 10, Issue 3, 2023 · pp. 1–5 Read article
-
Solid Waste Management System in Pabna Municipality of Bangladesh: A Case Study
Abstract: The increasing quantity of solid waste is a growing environmental problem in many developing countries like Bangladesh. Solid waste is indiscriminately dumped on roadsides, near dustbins and into open drains thus leading to serious health risk and degradation of living environment for people of most cities like Pabna. This paper presents the existing solid waste management system of Pabna municipality. Primary data were collected from householders and waste workers through …
Published in Recent Trends in Civil Engineering & Technology · Vol. 10, Issue 1, 2020 · pp. 18–24 Read article
-
Determination of Well Loss and Aquifer Loss of New Construction Deep Water Well at Artesian Aquifer in Khulna City, Bangladesh
Abstract: This work studied the performance of water well installed as artesian aquifer in South Western Region of Bangladesh. The main activities were known to the properties of aquifer condition on that area. Well performance was also measured after development of water well. The well performance and aquifer performance were justified by Rorabaugh’s graphical methods. The total depth of drilling was 305 m from the ground level. Drilling was completed by …
Published in Recent Trends in Civil Engineering & Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
-
A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
-
Safety System Analysis of Nuclear Power Plant in Bangladesh
Abstract: In this paper, the safety system and safeguards of the model VVER-1000, which is a Gen-III pressurized water reactor, designed by ROASTAM and chosen to be implemented in Bangladesh, will be analyzed. Several predefined major faults have been set to demonstrate the performance in preventing the release of harmful radiation. From simulation results, it has been observed that for moderator dilution, the malfunction is neutralized within 115 sec, for turbine …
Published in Trends in Electrical Engineering · Vol. 6, Issue 3, 2016 · pp. 11–25 Read article
-
Computation of Remaining Serviceable Life (RSL) of Bituminous Concrete (BC) Surfaced Road Sections using Hdm-4 Model
Abstract: The road network is the basic component that facilitates free movement of traffic from one area to another. The road sections are constructed to facilitate traffic for their entire design life. Due to the insufficient maintenance and rehabilitation activities, road section deteriorates rapidly and rapid deterioration results in entire road section damage prior to its design life. This paper presents the methodology for computing remaining serviceable life (RSL) in years …
Published in Trends in Transport Engineering and Applications · Vol. 4, Issue 2, 2017 · pp. 8–15 Read article
-
Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDL
Abstract: The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 2, 2021 · pp. 14–19 Read article