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153 articles for “CMOS design”
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A Survey on Ultra Low Power Design Techniques for IOT Application
Abstract: AbstractInternet of Things (IOT) is evolving as technology’s megatrend, unlocking new opportunities and questions for the semiconductor industry. IOT sensing and actuation devices essentially should be low cost and also should deliver a complete System on Chip (SOC) solution capable of computation, security and wireless communication at very low power levels. The sub-threshold operation, Radio Frequency (RF) redesign, and extreme optimization techniques can minimize power consumption of IOT devices. This …
Published in Current Trends in Information Technology · Vol. 7, Issue 3, 2017 · pp. 9–16 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 42–54 Read article
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Comparative Analysis of Combinational Circuit Using Reversible Logic Based Techniques
Abstract: In the last few decades, due to the ever growing demand for portable and small sized devices, integrated circuits require electronic circuit design methods to implement integrated circuits with low power consumption. The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Adiabatic logic technique is one of the …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 30–33 Read article
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High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology
Abstract: In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In today’s digital world, IC plays a vital role in high-performance computing, communication, and many consumer electronics. IC manufacturing technology has scaled down to smaller device dimensions. This scaling has a great impact on the design of digital ICs. The main objective of the IC manufacturing technology is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 34–42 Read article
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High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Abstract: This paper focuses on the design and optimization of latch comparators for high-speed data converter applications. The performance of different comparator architectures is compared in terms of speed, power consumption, and noise performance. The proposed latch comparator architecture uses a preamplifier to boost gain and sensitivity, and a latch to store the output signal. The latch comparator design is optimized for low power consumption and high speed, and is implemented …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 23–32 Read article
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Comparative Analysis of Low-Power Adiabatic Techniques
Abstract: In today’s modern era, new revolutionary designs are replacing old traditional bulky designs. Due to advancements in technology, low-power designs are in demand. Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on parameter changes. In this paper, the merits of adiabatic techniques are depicted on the basis of parameter variations. By the use of SPICE …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 53–58 Read article
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Design of Photonic Sensor for Driver Assistance
Abstract: AbstractA report from National Highway Traffic Safety Association, USA, states that 100000 police reported crashes are a result of driver fatigue. This figure would be quite mind boggling for developing nations, where work periods are usually extended without conducting detailed scrutiny. Sophisticated vehicles are equipped with sensors for assisting drivers and providing them with time-critical accident alerts. However, there is a need to develop cheap and reliable sensors for 24x7 …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 2, 2018 · pp. 14–23 Read article
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Exploring the Potential of Adiabatic Logic for Low Power Nano-scale VLSI Designs
Abstract: Low power dissipation has emerged as one of the main research areas due to the ongoing scaling down of device technology in the area of VLSI circuit design. Adiabatic logic gates are a practical answer to the rising demand for low power portable gadgets. Various adiabatic logic families, including 2N-2N2P, PFAL (Positive Feedback Adiabatic Logic), DCPAL (Differential Cascode and Pre-resolved Adiabatic Logic), and a suggested circuit centred on the PFAL …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 6–14 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 28–34 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article
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3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters
Abstract: Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper. Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 2, 2014 · pp. 1–8 Read article
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Current Controlled Oscillator Using FinFET
Abstract: A current-controlled oscillator using 18 nm FinFET technology is proposed in this study which consists of a Current Controlled Differential Difference Current Conveyor (CCDDCC) block to control the current. FinFET technology has better scalability and lower leakage current compared to traditional CMOS, which allows it to surpass the obstacles faced by CMOS-based oscillators. The suggested oscillator is suitable for electronic applications such as Phase-Locked Loop (PLL) systems, radio frequency (RF) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 3, 2025 · pp. 17–28 Read article
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A High Frequency and Power Efficient Memristor Emulator and Its Application
Abstract: This study presents a small, energy-efficient memristor emulator made for use at high frequencies. The proposed circuit has a simple design that only includes three n-type MOSFETs and a grounded capacitor. This means that there is no need for active components or DC biasing. This streamlined architecture not only makes things easier, but it also uses very little power, with dynamic and static power measured at 15.82 μW and 65.6 …
Published in International Journal of Electrical and Communication Engineering Technology · Vol. 3, Issue 2, 2025 · pp. 45–52 Read article
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A Neuromorphic-Inspired, Low-Power VLSI Architecture for Edge AI in IoT Sensor Nodes
Abstract: As the proliferation of Internet of Things (IoT) devices continues to rise, there is an increasing demand for real-time, energy-efficient artificial intelligence (AI) processing directly at the network edge. Traditional edge AI accelerators, often based on deep learning models like convolutional neural networks (CNNs), struggle to meet the ultra-low-power requirements of battery-constrained IoT sensor nodes. In response to this challenge, this study introduces a neuromorphic-inspired, low-power very- large-scale integration (VLSI) …
Published in Journal of Microelectronics and Solid State Devices · Vol. 12, Issue 2, 2025 · pp. 41–47 Read article
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Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Abstract: This paper describes a topology of voltage follower Class-AB Voltage Follower like Translinear voltage follower using MOS and DTMOS Transistor. The circuits are simulated in 90 nm technology. The results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. The analysis are made in terms of gain, bandwidth and transient response using ELDO spice, IC station and Design architect of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 64–70 Read article
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Implementation of a 4-Bit Synchronous Counter in SkyWater 130 nm CMOS Technology Using Open-Source EDA Tools
Abstract: As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 2, 2026 Read article
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit
Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article