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261 articles for “chip-off”
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A Reliable Routing Architecture and Algorithm for Network-on-Chip
Abstract: The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication through packet based networks. In NOC topology, routing algorithm and switching are main terminology. The routing algorithm is one of the key factors in NoC architecture. The routing algorithm which defines as the path taken by a packet between the source and the destination. The paper proposes a novel algorithm for a Network-on-Chip, which is based on packet …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 40–48 Read article
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Design and Fabrication of Semi-Automated Sugarcane Bud Chipper
Abstract: In today's competitive world, the production of agricultural products has to be accelerated. Agriculture is the particle of India. Almost all farmers in India face the problem of labor shortage. Wages of wages are increasing day by day, and agricultural products are increasing in the same way. The purpose of this project is to design and manufacture semi-automatic grinding machine of sugarcane buds for agriculture. To increase the efforts of …
Published in Journal of Mechatronics and Automation · Vol. 7, Issue 2, 2020 · pp. 14–16 Read article
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Survey of System-on-Chip Modular Test Approach
Abstract: The advancement in semiconductor technology over the past few decades has enabled the industry to develop new design and reuse methodologies referred as System-on-chip (SoC) design. These typically integrate heterogeneous mix of various complex analog and digital cores, with all their necessary electronic circuitry. The recent advancements have led to the use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance, minimum average interconnect length, reduced …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 56–70 Read article
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Low Power and Area Efficient System Achieved by using Efficient Virtual Channels on Network on Chip
Abstract: In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in a router are included. However, if the router includes five I/O ports, then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, smart power-saving (SPS), for low power consumption and low area in virtual channels …
Published in Journal Of Network security · Vol. 4, Issue 2, 2016 · pp. 36–41 Read article
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Advancing IoT Connectivity through Very Large-Scale Integration of Semiconductor Technology
Abstract: The term "integrated circuit" as it is currently used typically refers to a monolithic IC, which is significantly different from an HIC in that the former is created by joining several components on a substrate, while the latter is created in a sequence of steps using a single wafer that is subsequently divided into chips. Hybrid chips are perfect for complicated applications in sectors like artificial intelligence (AI), the Internet …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 54–63 Read article
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Literature Survey of On-chip Architectures and Arbitration Algorithms
Abstract: Today micro-electronic products are influencing the ways of communication, learning and entertainment. The key driving force for the developments during decades is the System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips. Not only functionally enriched, these products such as mobile phones, notebooks and personal handheld sets are becoming faster, smaller-in-size, larger-in-capacity, lighter-in-weight, lower-in-power-consumption and cheaper. In this survey, communication architectures of SoC are discussed whose design …
Published in Journal of Microcontroller Engineering and Applications · Vol. 4, Issue 1, 2017 · pp. 17–23 Read article
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Reducing Cell Density Congestion Issue in Chip Design
Abstract: AbstractThe congestion issues reduce with the help of shrinking process technologies. Here, typical placement objectives involve reducing cell density congestion in a chip design. Congestion reducing is the least understand; however, it models route ability most accurately. The congestion issue is cell density (commonly believed to be very effective) does not always work well, so here by applying the partial block technique for the cell density is among the best …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 3, 2019 · pp. 11–17 Read article
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The Emerging Technologies in the Field of Semiconductors Along with the Use of the System on Chip
Abstract: An entire electronic or computer system can be combined onto a single platform using a system on chip, which is effectively an integrated circuit. The primary objectives underlying the development of this system on chip are to decrease energy waste, cut costs, and decrease the area occupied by massive systems. Students can understand and experience many methods utilised at each level of the design hierarchy using this strategy. The expansion …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 8–15 Read article
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Design and Simulation of Proximal Convoluted Tubule Flow Kinetics for Kidney-on-chip Applications
Abstract: The primary function of human kidney is purifying the impure blood in the body. In addition to this, kidney performs balance homeostasis, solute balance and blood pressure maintenance. Proximal convoluted tube (PCT) is a primary part in the nephron which plays a crucial role in the excretion, secretion and re-absorption of solutes and proteins. While performing all these functions, kidneys tends to get affected in several ways leading to failure …
Published in Journal of Operating Systems Development & Trends · Vol. 7, Issue 1, 2020 · pp. 14–21 Read article
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Comparative Analysis of Natural vs. Synthetic Antioxidant during Deep-Fat Frying of Potato Chips
Abstract: The aim of this study was the comparative analysis of natural antioxidant derived from rosemary extract, mixed tocopherol, alpha tocopherol, Ascorbyl Palmitate with synthetic antioxidant (TBHQ) during deep fat frying. Palm oil with tertiary butylhydroquinone (TBHQ), a synthetic antioxidant, and palm oil without any added antioxidant were used as positive controls. Thermo-oxidative transformations were measured according to various physical and chemical parameters. Total polar compounds (TPC), free fatty acids (FFA), …
Published in Research & Reviews : Journal of Food Science & Technology · Vol. 4, Issue 2, 2015 · pp. 1–12 Read article
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A Novel Approach Based On-Chip High Speed Optical Interconnection Network
Abstract: On-chip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication problem and obtain high-performance integrated circuits. On-chip interconnects are an important performance limiting factor in present day VLSI design. Performance optimization has always been a critical step in the designing of integrated circuits. In this paper, an optical interconnect in 1550 nm range is being implemented using opti-system software. A novel approach is …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 41–48 Read article
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A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network
Abstract: Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately, solve the communication problem, and to obtain high-performance integrated circuits. In this study, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to fulfill the requirements of silicon-based ICs must satisfy to successfully perform copper electrical interconnects (IEs). Keywords: Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonicsCite this ArticleAbhishek Sharma, Sudhir Kumar …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 36–44 Read article
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Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
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Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article
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Digital PID Chip Design and FPGA Synthesis
Abstract: The industrial applications follows the control operations based on closed loop system due to their stability and controllable desired response. The proportional-integral-derivative (PID) controller is one the most adopted controller in dynamic control systems. In some industries, specific PID controllers are used for particular control. The PID control is used for early days staring form mechanical and pneumatic designs, and its implantation is based on analog circuits using transistors. There …
Published in Recent Trends in Parallel Computing · Vol. 5, Issue 2, 2018 · pp. 13–19 Read article
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Experimental Analysis of Cutting Forces Under Different Machining Parameters and Carbide Inserts During Turning of Hardened AISI 4340 Steel
Abstract: Turning of hardened materials with an advanced coated carbide insert has numerous advantages over the grinding process, e.g., reduced process cost, high material removal rate, and less environmental concern due to the elimination of the cutting fluid. Process parameters in conventional machining operations like cutting speed, feed, and depth of cut play the most crucial role behind the generation of heat which also leads to microstructural changes, improved tool life, …
Published in Journal of Polymer & Composites Read article
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Digital Communication Receiver CMOS Chip Design
Abstract: RF receivers are such electronic devices that discrete radio signals from one another and transform specific signals into respective audio, video, or data formats. It uses an antenna to receive transmitted radio signals and a tuner to separate a specific signal from all of the other signals that the antenna receives. Detectors or demodulators at that moment extract information that was programmed formerly to transmission. There are numerous customs to …
Published in Recent Trends in Electronics Communication Systems · Vol. 1, Issue 3, 2014 · pp. 16–21 Read article
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Finite Element Simulation and Experiment of Machining of Steel: A Review
Abstract: As a propelled producing innovation, which has been created quickly as of late, rapid machining is generally connected in numerous commercial enterprises. The chip arrangement amid fast machining is a convoluted material twisting and expelling process. In examination region of fast machining, the expectation of chip morphology is a hot and troublesome subject. A limited component technique in light of the product ABAQUS which includes Johnson-Cook material model and crack …
Published in Journal of Production Research & Management · Vol. 6, Issue 2, 2016 · pp. 13–19 Read article
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Study on Digital Forensics in IoS Devices
Abstract: Digital forensics has progressed rapidly but much more is required, including developing more sophisticated techniques for acquiring and analyzing digital evidence, increasing scientific rigor in our work, and also professionalizing the field. This paper surveys the area of digital forensics, with the aim of systematizing the existing techniques which is useful for promoting future research. The authors first present the unique aspects and also the tools used in digital forensics. …
Published in E-Commerce for Future & Trends · Vol. 1, Issue 1, 2014 · pp. 21–28 Read article
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A Survey on Various Study for SRAM Cell Topologies
Abstract: Abstract: In order to meet performance demands continuous derivative, the amount of on-chip memory or microprocessors and system-on-chip is increased. As much as 70% of the chip area is now given to the embedded memory, which is mainly realized by the static random access memory (SRAM). Due to the large size of the SRAM, their energy performance and leakage performance and leakage dominate total energy consumption of the chip. The …
Published in Journal of Software Engineering Tools & Technology Trends · Vol. 6, Issue 3, 2019 · pp. 1–8 Read article