Search
36 articles for “Spice simulation”
-
Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
-
Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article
-
Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
-
1-Bit Full Adder's Analysis and Comparison
Abstract: The full adder circuit forms the basis of majority of digital circuits. Improvement in a basic full adder circuit in terms of area, power and delay affect the performance of whole system. It becomes compulsory to investigate and analyze the performance of implementation of full adder circuit in literature, till now. In this paper, a study is carried out to look into performance parameters of full adder circuit using different …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 1–6 Read article
-
CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
-
Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver
Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article
-
Design of CMOS AM Modem for Wireless Sensors
Abstract: A design of amplitude modulated (AM) modem, compatible to CMOS technology for its monolithic integration with either wireless microsensors or other sources of baseband signals, is presented in this paper operating in different frequency bands. Circuits functional in different operating conditions are considered in the paper to satisfy the requirement from low- to high-speed signals produced either from the wireless sensor or other signal source to be modulated on a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 44–51 Read article
-
T-π Network Simulation and Thevenin- Norton Equivalent Circuit Values From Laplace Description Using Pspice Software
Abstract: From the conversion methods of T-π (star-delta) for impedances circuits, the behavioral modeling of Pspice simulation program is used to obtain equivalent circuits using LAPLACE option. The conversions are verified for two types of circuits by obtaining AC values of voltages and currents at various nodes and branches using Pspice computer simulations. There are many ways of expressing Thevenin/Norton equivalent circuit parameters such as (a) as real numbers for pure …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 2, 2022 · pp. 43–58 Read article
-
Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology
Abstract: Paper describes the performance analysis, implementation and characterization of low-power and high-speed shared charge clocked-latch based comparator using 90-nm technology. There are two different topologies of the comparator viz. impedance dividing and differential current sensing comparators are combined to take the advantages and use their good features. The main focus of design is on improvement in speed by sharing charge and reduction in power dissipation. The topology is implemented in …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 20–26 Read article
-
Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Abstract: This paper describes a topology of voltage follower Class-AB Voltage Follower like Translinear voltage follower using MOS and DTMOS Transistor. The circuits are simulated in 90 nm technology. The results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. The analysis are made in terms of gain, bandwidth and transient response using ELDO spice, IC station and Design architect of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 64–70 Read article
-
Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
-
Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell
Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article
-
Three Techniques for DC Thevenin Resistance Using Pspice Simulation
Abstract: A time-domain method for certain types of excitations is proposed to determine Thevenin equivalent circuit for a circuit with resistors and dependent/independent sources. SPICE/Pspice model descriptions for resistors at constant temperature and dependent source are used. Instead of making the energy sources zero (as in frequency domain) the sources in time domain are described using model description cards available for time-domain current/voltage sources at the same time evaluating circuit for …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 1, 2025 · pp. 1–8 Read article
-
Equivalent Linear Circuit for Thevenin and Norton Representation Using Superposition Theorem
Abstract: Using superposition theorem and knowing the Thevenin representation consisting of resistor, independent DC source of a network an equivalent DC network is obtained using SPICE software with linear circuit elements and independent sources and is verified. Also, similarly from the Norton representation, equivalent circuit is obtained. A procedure with Pspice methods to obtain unknown circuit elements using reciprocity theorem is described. Possible examples for (a) only resistive networks and (b) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 2, 2024 · pp. 1–6 Read article
-
Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology
Abstract: A wide tuning range, low phase noise and low jitter 100 MHz Voltage-Controlled Oscillator (VCO) for DPLL was designed and implemented by 45 nm CMOS process technology using LT spice. There was a relation between the frequency tuning range, phase noise, and jitter at output of the VCO after linearizing the gain. Simulations using PTM 45 nm CMOS process technology shows, that a wide operation frequency range (tuning range) from …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 81–89 Read article
-
Designing and Simulation of Novel 6T CNT Based Schmitt Trigger on 32 nm Regime
Abstract: With the advancement of technology, we are needed to make the circuits more efficient, and for this, less leakage current and leakage power circuits are needed. Taking this into account, a model of Schmitt trigger using C-MOS (complementary mosfet) and CNT (Carbon Nano Tube) has been compared. We have worked on C-MOS and CNT circuits by using H-SPICE software. As a result, it is found that leakage current and leakage …
Published in Journal of Control & Instrumentation · Vol. 9, Issue 2, 2018 · pp. 1–4 Read article