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30 articles for “SPICE Circuit Simulation”
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Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
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True Random Number Generators Using A Postprocessor, Jitter Metastability, Tree-based Interleaver & Low-power CMOS inverter Circuit prototype technology: An Efficient Analysis
Abstract: TRNGs (True Random Number Generators) are cryptographic primitives that generate random numbers for critical operations. The goal of this study is to create a TRNG using a ring oscillator, analyse different calibration generating ways using VHDL spice simulation, and investigate the TRNG's essential design features, such as area, entropy, and power/energy consumption, using suggested and published methods. Random ones and zeros are produced using RO jitter and DCM frequency fluctuations. …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 66–76 Read article
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Comparative Analysis of Low-Power Adiabatic Techniques
Abstract: In today’s modern era, new revolutionary designs are replacing old traditional bulky designs. Due to advancements in technology, low-power designs are in demand. Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on parameter changes. In this paper, the merits of adiabatic techniques are depicted on the basis of parameter variations. By the use of SPICE …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 53–58 Read article
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Designing and Simulation of Novel 6T CNT Based Schmitt Trigger on 32 nm Regime
Abstract: With the advancement of technology, we are needed to make the circuits more efficient, and for this, less leakage current and leakage power circuits are needed. Taking this into account, a model of Schmitt trigger using C-MOS (complementary mosfet) and CNT (Carbon Nano Tube) has been compared. We have worked on C-MOS and CNT circuits by using H-SPICE software. As a result, it is found that leakage current and leakage …
Published in Journal of Control & Instrumentation · Vol. 9, Issue 2, 2018 · pp. 1–4 Read article
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Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Abstract: This paper describes a topology of voltage follower Class-AB Voltage Follower like Translinear voltage follower using MOS and DTMOS Transistor. The circuits are simulated in 90 nm technology. The results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. The analysis are made in terms of gain, bandwidth and transient response using ELDO spice, IC station and Design architect of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 64–70 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Review of Low Power Johnson Counter
Abstract: Due to the use of clock gating the authors have achieved a power reduction of 37.12 to 41.08% for different frequencies. The authors have run T-Spice simulations for conventional design and clock-gated Johnson counter design. There is a huge difference in the power consumption of the two designs. The clock-gating logic gives this change. And as a 2-input flip-flop is used instead of 3-input flip-flop plays a remarkable role in …
Published in Journal of Microelectronics and Solid State Devices · Vol. 2, Issue 1, 2015 · pp. 13–17 Read article
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Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell
Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article
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A Low Power Low Voltage High Performance CMOS Current Mirror with Improved Output Impedance
Abstract: The current mirrors are very useful in the designing of mixed mode and analog circuits. A high performance CMOS current mirror with high output impedance and a small power supply close to the threshold voltage of the transistor are presented in this paper. For achieving the high output impedance, an additional transistor is used at the output section of the current mirror. This additional transistor will improve the output impedance …
Published in Journal of Microelectronics and Solid State Devices · Vol. 3, Issue 1, 2016 · pp. 14–19 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article