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43 articles for “Verilog-A”
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Computer Modeling of Organic Thin Film Transistors (OTFTs) using Verilog-A
Abstract: AbstractOrganic electronics has drawn considerable attention of the researchers with organic thin film transistors (OTFTs) as key components for various applications. Compared to the silicon industry where public models are well defined and commonly used to provide designers with a relative good description of any process, organic devices are still lacking for their complete device models that can fully describe their electrical characteristics. Therefore, compact model development for OTFTs is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 1–7 Read article
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Verilog-Based Image Processing on Field Programmable Gate Arrays: Design and Implementation
Abstract: Integrated circuits known as Field Programmable Gate Arrays (FPGAs) are frequently offered for sale off the shelf. They are known as "field programmable" because, following manufacture, they enable users to modify the hardware to satisfy particular use case needs. This makes it possible to update features and correct bugs in-place, which is very helpful for remote deployments. Configurable logic blocks (CLBs) and a series of programmable interconnects are features of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 13–26 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Abstract: The integration of image processing algorithms into hardware platforms, particularly FPGAs, presents a compelling opportunity for achieving high performance, low latency, and power efficiency in real-time applications. This study focuses on designing and implementing Verilog HDL-based optimal image processing methods for FPGA-based systems. The study explores the development of core algorithms, including edge detection, image enhancement, and adaptive filtering, to maximize resource utilization and processing speed on hardware platforms. Key …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 46–53 Read article
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Study and Implementation of I2C Bus Controller using Verilog HDL
Abstract: AbstractInter Integrated Circuit is a Philips semiconductor. This bus is a two-wire, low to medium speed, correspondence transport created by Philips Semi-conductors. It gives capable chip to chip correspondence. I2C is found in for the most part specialized devices. Two bus lines are required SDA and SCL (serial information and serial clock line) both should be pulled up with a resistor to +Vdd. Serial, 8-bit arranged, bidirectional information exchanges can …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 1, 2017 · pp. 29–33 Read article
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Automatic Coffee Making Machine Using Verilog HDL
Abstract: This Paper focuses on the design and implementation of a Coffee Machine using Verilog, aimed at understanding how real-life machines can be controlled using digital logic. In daily life, a coffee machine works by taking user inputs, processing them, and giving the required output such as preparing coffee. The main objective of this project is to design a simple digital system that controls the basic working of a coffee machine. …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 1, 2026 · pp. 18–24 Read article
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DESIGN OF SCRAP COLLECTION AND REWARD MACHINE USING VERILOG HDL
Abstract: The growing amount of waste produced in urban environments has led to a demand for effective and automated recycling solutions. In this paper, a scrap collection and reward machine is designed and implemented using the Verilog Hardware Description Language (HDL). The proposed system is developed to provide a reliable and automated approach for managing recyclable materials while motivating users through a reward-based mechanism. The design includes scrap input interfaces, a …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 1, 2026 · pp. 37–45 Read article
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Design of an Automatic Device Controller Based on Temperature Sensing by Using Verilog HDL Targeting an FPGA
Abstract: To get a single controller that is capable to produce some control signal depending on sensing temperature is getting popularities for industrial and home applications. In this paper uses an LM34 Precision Fahrenheit Temperature Sensor IC and an ADC0820 8-Bit, high-speed, µP-compatible flash A/D converter IC in order to design and implement the mentioned controller onto a SPARTANTM-II Field Programmable Gate Array (FPGA) by using DigilentTM Pegasus SPARTAN-II FPGA Board, …
Published in Journal of Control & Instrumentation · Vol. 3, Issue 1-3, 2012 · pp. 6–16 Read article
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Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation
Abstract: This paper introduces a novel and enhanced Gabor filter design aimed at addressing the demands of image processing applications using the Verilog Hardware Description Language (HDL). Specifically, it leverages the Reconstruct Gabor filter technique to elevate the performance and quality of standard image outputs. The primary objective of this research endeavor is to simplify the study, conduct an in-depth analysis, and substantially enhance the design's efficiency, all while ensuring the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 40–46 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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RTL to GDSII Implementation UART using Verilog and Cadence tools
Abstract: The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 1–7 Read article
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Design of a Verilog HDL-Based Advanced Intelligent Automatic Railway Gate Control System
Abstract: Human mistake, sluggish reaction times, and manual gate operation are common causes of railway level crossing accidents. This project suggests an Intelligent Automatic Railway Gate Controller made with Verilog HDL and simulated in Xilinx Vivado to lessen these mishaps. With the goal of improving safety at unmanned railway crossings, the system is intended to offer a dependable and entirely automated solution. Without human interaction, the railway gate is automatically controlled …
Published in International Journal of Electronics Automation · Vol. 4, Issue 1, 2026 Read article
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Verilog Implementation of a Turbo Encoder and Decoder with MAP-Based Decoding
Abstract: The most significant achievement in coding theory is the turbo codes which are forward error correction codes developed in 1993. By using two simple recursive systematic convolutional codes in parallel we can achieve near-capacity performance in transmission system which was defined by Shannon-Fano. By using iterative decoding structure near-capacity performance is possible with a relatively easy decoding complexity, using a soft in soft out (SISO) maximum a posteriori (MAP) decoding …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 19–24 Read article
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Published in International Journal of VLSI Circuit Design & Technology Read article
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Triangular Waveform Generation using Mixed Signal Modeling
Abstract: The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of analogue and mixed signal circuits to be described with a more lucid way as compared to the conventional circuit-level simulators. Mixed-signal simulators are thus providing a new platform for more efficient modeling of mixed signal that contains both the analogue and discrete features which was not previously possible. The non-linear characteristics of many circuits are still …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 8–17 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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Coverage Driven Verification of Synchronous FIFO using UVM
Abstract: FIFO (first in first out) is a memory array in which the data written first into the memory will be read first with the help of the control signals read and write where the control signal write is used to write the data into the memory and the control signal read is used to read the data from the memory. To avoid the memory overflow and to know that whether …
Published in Recent Trends in Electronics Communication Systems Read article
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Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics
Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article
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Different Compressor Adders
Abstract: AbstractMultipliers are one of the main blocks which decide the circuit performance as well as computation speed. In multiplication, addition of partial products contributes most to the circuit delay, power, and area. In this project, compressor adders are used to reduce this delay. Hence, compressors are a major part of the multiplier circuit that decides the overall speed of the system. For high-speed processing and higher systems, a huge number …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 19–26 Read article
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Practical Implementation of Network Switch on FPGA
Abstract: AbstractA network switch is a hardware device, which is used for device communication within a network. It uses a packet-switching mechanism to receive and transmit data to the target device. Network switches contain multiple ports that use media access control (MAC) address for transmitting data at the data link layer (layer 2) of the Open Systems Interconnection (OSI) model. This research aims to design a network switch on FPGA to …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 7, Issue 1, 2020 · pp. 14–19 Read article