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10 articles for “Xilinx System Generator”
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An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator
Abstract: This paper aims at designing a Field programmable gate array (FPGA)-based proportional, integral derivative (PID) controller in a servo-actuated control system. In the conventional method of implementing control systems in FPGA, there is no interaction between the controller and the system except for the final stage of implementing control system in the hardware. The proposed methods provide approaches for analyzing the performance of the controller and system in MATLAB simulink …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 1–6 Read article
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Hardware/Software Co-Simulation of Gradient-based Edge Detectors: A Comparative Study
Abstract: Edge detection, a segmentation technique, produces an edge map that contains important information about the image. We realized Gradient-based Edge Detection Algorithms in FPGA hardware utilizing Hardware-Software Co-Simulation with the help of Simulink (Mathworks) and System Generator (Xilinx). We explored and utilized different gradient based edge detection operators Sobel-Fieldman, Robert and Prewitt Operator. After comparative analysis, we found both Sobel and Robert operators among the best with hardware realization of …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 2, Issue 3, 2015 · pp. 30–37 Read article
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Hardware Implementation of Configurable Multi Image Fusion
Abstract: Multifocus images make it difficult to describe a scene accurately. Hence, the fusion of two or more images forms a good solution in order to obtain a new image containing more appropriate description of the scene than any of the input images. This paper presents a method of image fusion which uses stationary wavelet transform and fuzzy logic. By overcoming the disadvantages of discrete wavelet transform such as downsampling and …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 6–15 Read article
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation
Abstract: Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 55–61 Read article
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Study and Design of Reconfigurable Processor Peripherals using Xilinx Tools
Abstract: AbstractXilinx Platform Studio used in this paper to create a reconfigurable processor system. The Xilinx Embedded Development Kit (EDK) software allows mapping processor of a Microblaze plus several on-chip peripheral bus (OPB) peripherals. The EDK bridges the gap between Hardware (HW) and Software (SW), flows by providing a single HW/SW design environment. Xilinx ISE is to create a top-level design hierarchy. It extends a fully software architecture by generating and …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 17–23 Read article
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Performance Analysis of AES Encryption Using LFSR-Based Key Expansion in VLSI
Abstract: Secure data transmission has become increasingly important with the rapid growth of digital communication and embedded systems. Protecting sensitive information from unauthorized access requires reliable cryptographic solutions. Among the available techniques, the Advanced Encryption Standard (AES) is widely recognized for its strong security and efficient implementation in both hardware and software environments. In this work, the design and performance evaluation of an AES-based crypto processor with LFSR-driven key expansion is …
Published in Recent Trends in Electronics Communication Systems · Vol. 13, Issue 1, 2026 · pp. 23–31 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Low-Power Reconfigurable Digital Filter Design Using FPGA for IoT Edge Devices
Abstract: The rapid evolution of the Internet of Things (IoT) has led to an exponential increase in the deployment of edge devices that continuously process real-time sensor data under strict power, latency, and computational constraints. Digital filtering remains a critical operation in these devices, supporting tasks such as noise removal, data conditioning, and feature extraction for intelligent decision-making. However, conventional filter implementations on microcontrollers or fixed digital signal processors often struggle …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 23–34 Read article
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Design and RTL Implementation for AHB-APB Bridge on SoC
Abstract: The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 44–52 Read article
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Parallel Cyclic Redundancy Check Generator for Applications
Abstract: CRC is assuming a primary part in the systems administration environment to recognize the mistakes. With testing the pace of transmitting information to synchronize with velocity, it is important to build pace of CRC Generation. Generally builds are acquainted with the cyclic repetition check (CRC). Numerous realize that it is utilized as a part of correspondence conventions to recognize bit mistakes and that it is basically a rest of the …
Published in Recent Trends in Parallel Computing · Vol. 3, Issue 2, 2016 · pp. 31–33 Read article