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336 articles for “STM-32 MCU”
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STM32 MCU-based System for Testing Parameters of Lithium-Ion Batteries
Abstract: The Automobile manufacturing sector’s fast-paced advancement has raised concerns regarding energy conservation and reduction of emissions. To address this, electric vehicles have become a crucial solution, with lithium batteries as a core component. This paper presents the designing a test system for measuring the parameters of lithium battery, with the STM32F411RE micro controller as the crucial element. In contrast to the domestic market, the parameter detecting system for lithium-ion batteries …
Published in Journal of Microelectronics and Solid State Devices · Vol. 10, Issue 2, 2023 · pp. 18–27 Read article
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Smart Trolley System for Retail Stores: A Node MCU-Based Approach for IoT Integration
Abstract: This project report presents the design, development, and implementation of an RFID and IoT-based Smart Trolley System. The project is a collaborative effort undertaken by a group of dedicated individuals. The primary objective is to enhance the traditional shopping experience by leveraging advanced technologies to improve efficiency, convenience, and data analytics in retail environments. The Smart Trolley System integrates Radio-Frequency Identification (RFID) technology and the Internet of Things (IoT) to …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 2, 2024 Read article
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AI Powered Fault Detection in DC Motor using STM32
Abstract: This work presents the design and implementation of an embedded artificial intelligence system for real-time fault detection in a direct current (DC) motor using the STM32 Nucleo- F411RE microcontroller. The objective of the study is to develop a low-cost and efficient predictive maintenance solution capable of identifying abnormal motor behavior at an early stage. Vibration and temperature signals are acquired using an MPU6050 sensor and processed directly on the microcontroller …
Published in Journal of Control & Instrumentation · Vol. 17, Issue 1, 2026 · pp. 39–49 Read article
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IoT and Node MCU based Smart Logistics
Abstract: Logistics plays a key role in global economies, encompassing the planning, implementation, and control of goods movement. Traditional logistics systems often suffer from inefficiencies, such as manual tracking, delays, and lack of real-time visibility, leading to increased costs and environmental waste. The advent of IoT has revolutionized this sector by enabling interconnected devices to gather and argument data seamlessly. At the heart of many IoT applications is Node MCU. It …
Published in Recent Trends in Sensor Research & Technology · Vol. 12, Issue 2, 2025 · pp. 38–50 Read article
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Automatic Railway Horn System Using Node MCU
Abstract: The Automatic Railway Horn System (ARHS) presented in this project employs techniques to dynamically adjust the frequency of the train horn based on various parameters such as train speed, proximity to crossings, and other safety considerations. Traditional railway horn systems often lack adaptability and may not adequately address changing environmental conditions. The proposed ARHS aims to enhance safety and minimize noise pollution by intelligently modulating the horn frequency in real-time. …
Published in Journal of Control & Instrumentation · Vol. 15, Issue 1, 2024 · pp. 11–19 Read article
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Analysis of Signal Delay in Carbon Nano Tube based Interconnects at 32 nm Technology Node
Abstract: AbstractIn the present world demand for portable devices and high speed processor is rising which brings out a challenging issue of scaling for designers. In this paper, we have presented the effect of copper and CNT based interconnects for different length at 32 nm technology node. The performance of both types of interconnects are analyzed and compared in form of propagation delay. Propagation delay in interconnects between the elements is …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 20–26 Read article
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RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor
Abstract: This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 1–10 Read article
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Designing and Simulation of Novel 6T CNT Based Schmitt Trigger on 32 nm Regime
Abstract: With the advancement of technology, we are needed to make the circuits more efficient, and for this, less leakage current and leakage power circuits are needed. Taking this into account, a model of Schmitt trigger using C-MOS (complementary mosfet) and CNT (Carbon Nano Tube) has been compared. We have worked on C-MOS and CNT circuits by using H-SPICE software. As a result, it is found that leakage current and leakage …
Published in Journal of Control & Instrumentation · Vol. 9, Issue 2, 2018 · pp. 1–4 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Signal Integrity Analysis of Single Walled Carbon Nano Tube based Interconnects at 32 nm Technology Node
Abstract: The rising demands for ultra-high-speed processors and portable devices have made the transistor and interconnect scaling a challenging issue in present days. In this work, the impedance parameter of copper and CNT based interconnects are calculated at 32 nm technology node for different lengths. The performances of CNT based interconnects are analyzed and compared with Cu based interconnects in terms of crosstalk. The conventional copper interconnects are not able to …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 33–42 Read article
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An Optimized 32 bit Carry Select Adder Using Modified BEC
Abstract: AbstractAdders play a major role in addition of numbers, multiplications and other advanced processors’ design. Among the conventional adder structures, carry select adder is known to be fastest adder. This adder circuit is used for the design of high speed processors. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. CSLA circuit for 8, 16, 32 bits is designed without multiplexer …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 27–32 Read article
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Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
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Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology
Abstract: In this paper power consumption of Gated diode DRAM (Dynamic Random Access Memory) cells are carried out. This analysis is carried out on 32 nm scale. The DRAM cell used here are 3T1D and 2T1D DRAM cell. Static, total average and transient power for both types of cells are simulated in order to have a comparison of their performance on the same technology. A comparative study of different types of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 19–23 Read article
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RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools
Abstract: Exploring the RTL-to-GDS implementation of a high-speed on-chip 32:1 serializer, this study investigates the integration of open-source tools within VLSI design, emphasizing sustainable practices in the semiconductor industry while operating at the nanometer scale. Addressing methodologies for optimizing power consumption and chip area utilization, particularly focusing on efficient use of non-renewable resources. The study is set against the backdrop of advanced 7nm FinFET technology, critical for enabling efficient data transmission …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 1–10 Read article
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32-bit Single Cycle MIPS RISC Processor
Abstract: In this report, I have written a Verilog HDL code for the MIPS 32-bit single-cycle RISC Processor and simulate the same. I have derived the result in four points first in terms of resource utilization, an RTL design view, TTL design view, and perform simulation on emulator using machine code. The topics I have cover the report are how to define instruction set for RISC architecture? Designing of various digital …
Published in Current Trends in Signal Processing · Vol. 12, Issue 1, 2022 · pp. 29–37 Read article
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An Efficient Tree Structure 32-Bit Brent-Kung Adder for Reducing Time Delay and Memory Utilization
Abstract: AbstractBrent-Kung adder is such of the parallel prefix adders secondhand for speeding of the operation. Parallel prefix adders are the fast adders and dig the arithmetic operations at the expeditious rate. Most Industries are like TMSC, Texas, are used by parallel prefix adders seeing of their advantages compared to a variance adder. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a campaign for increasing the speed …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 29–35 Read article
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Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node
Abstract: In this article an analysis of carbon nanotube field effect transistor based ring oscillator is performed. After analysis it was found that carbon nanotube transistor consumes less power in comparison to silicon transistor. CNFET is one possible candidate to substitute silicon-based integrated circuit (IC) technology, as the performance increase of conventional transistors witnessed during the last decades will arrive at its ultimate limits in the near future. Its present progress …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 51–54 Read article
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Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
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A 32-Bit Booth Multiplier Design Using GDI Logic Style
Abstract: Gate diffusion input (GDI) is the newest technology of designing a low-power digital combinational circuit. This logic allows reducing power dissipation, delay and area of any digital logic circuit. The gate diffusion input logic allows implementation of a wide range of any complex logic function. These functions can be realized using only two transistors. This technique is preferred for designing fast using less number of transistors while improving logic level …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 1–5 Read article
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Internet of Things based Car Parking System using ESP- 32 and Blynk
Abstract: The security of the vehicles at the populated places has always been an area of concern. At many crowded places where a number of vehicles enter and exit every day, the security has to be taken into account so that chaos is reduced by using an efficient model. This paper shows the implementation of an Internet of Things based car parking system which consists of electronic components such as infrared …
Published in Current Trends in Signal Processing · Vol. 12, Issue 1, 2022 · pp. 21–28 Read article