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10 articles for “RISC Processor”
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
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Design of 16-bit Pipelined RISC Processor
Abstract: This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 32–37 Read article
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32-bit Single Cycle MIPS RISC Processor
Abstract: In this report, I have written a Verilog HDL code for the MIPS 32-bit single-cycle RISC Processor and simulate the same. I have derived the result in four points first in terms of resource utilization, an RTL design view, TTL design view, and perform simulation on emulator using machine code. The topics I have cover the report are how to define instruction set for RISC architecture? Designing of various digital …
Published in Current Trends in Signal Processing · Vol. 12, Issue 1, 2022 · pp. 29–37 Read article
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Architectural Evolution of RISC Processors: From Early Research Prototypes to Modern Industrial Implementations
Abstract: This paper surveys the architectural evolution of Reduced Instruction Set Computer (RISC) architectures from early research prototypes to modern industrial processors, tracing four decades of design refinement across academic, embedded, server, mobile, and open- hardware ecosystems. Core ISA principles, pipeline evolution, compiler–hardware co-design, and quantitative performance modeling are analyzed through four representative industrial implementations: MIPS 74K, SPARC T4, ARM Cortex-A72, and SiFive U74 (RISC-V). Each processor is examined in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 29–39 Read article
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Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDL
Abstract: The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 2, 2021 · pp. 14–19 Read article
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RTL-to-GDSII Flow Optimization for Low-Power 32-bit RISC-V Processor
Abstract: This paper presents the implementation and optimization of a 32-bit RISC-V processor, transitioning from Register Transfer Level (RTL) design to final GDSII using Synopsys Fusion Compiler over 32nm technology node. The processor architecture is based on the RV32I base instruction set and incorporates a 5-stage pipeline to achieve a balanced trade-off between performance and design complexity. The design methodology involved RTL synthesis, gate-level netlist generation, and successive physical design stages …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 3, 2025 · pp. 1–10 Read article
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Fault Detection Attainment for Embedded Cores based on Software Test Routines
Abstract: The test circuitry is designed in built-in-self-test (BIST) technique involves a system that applies the test signals and observes the corresponding system response. In this technique, the framework is embedded directly into the system hardware. The testing process performs efficiently, fastly and more economically than using an external test setup. Self-testing of embedded processors based on the test routines is an emerging method, since it employs a test resource partitioning …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 1–6 Read article
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The Emerging Technologies in the Field of Semiconductors Along with the Use of the System on Chip
Abstract: An entire electronic or computer system can be combined onto a single platform using a system on chip, which is effectively an integrated circuit. The primary objectives underlying the development of this system on chip are to decrease energy waste, cut costs, and decrease the area occupied by massive systems. Students can understand and experience many methods utilised at each level of the design hierarchy using this strategy. The expansion …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 8–15 Read article
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article