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5 articles for “Majority Gate Logic”
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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A Majority Function Based Full Subtractor
Abstract: In the present landscape of very large-scale integration (VLSI) technology, the imperative to implement Boolean functions with minimal gate count remains a cornerstone of efficient circuit design. This pursuit has only grown more critical with the evolution of low-power design strategies, which now offer significantly enhanced benefits compared to traditional approaches. The trifecta of performance, affordability, and dependability continue to drive innovation in this field, shaping the trajectory of technological …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 8–14 Read article
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The Role of Majority Functions in Enhancing Full Subtractor Performance in High-Density Logic Circuits
Abstract: In the present trend of very large-scale integration (VLSI) technology, implementing a Boolean function with the fewest number of gates (logic) has always been important. Low power design strategies now provide much more benefits than in the past. Performance, affordability, and dependability may be key issues in this area of technology design. Power dissipation is now recognized as a crucial component in the development of competitive market areas such wireless …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 2, 2024 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Intelligent automated railway crossing gate control system
Abstract: The high incidence of accidents at railway level crossings due to human errors and lack of proactive track monitoring is a challenge for rail safety in high-density networks. This paper proposes the development and validation of an intelligent automated railway crossing system- IARCS that leverages sensor fusion and IoT communication to eliminate human dependency and mitigate intrusion risks. The core system deploys an Arduino Uno for the purpose of primary …
Published in Journal of Microcontroller Engineering and Applications · Vol. 13, Issue 1, 2026 · pp. 20–28 Read article