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5 articles for “MTCMOS technique”
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Transistor Full Adder: A Comparative Performance Analysis
Abstract: AbstractIn this work the static energy recovery full adder named 10T13A with reduced 10 transistors is implemented. The fan in and fan-out of gates is also reduced by reducing number of transistors. Calculation of 10T13A full adder various parameters has been at 45 nm technology and compared with MTCMOS technique based 10T13A Full Adder. The active power has been calculated at 45 nm technology using Cadence Virtuoso Tool. Simulation results …
Published in Recent Trends in Electronics Communication Systems · Vol. 5, Issue 3, 2018 · pp. 22–31 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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Comparative Analysis of Different SRAM Cells Architecture at 70 nm
Abstract: There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 33–41 Read article
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Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Abstract: This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 53–61 Read article
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Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell
Abstract: The demand of high density VLSI circuits has been increasing as the size of ICs is becoming small day by day. It has been seen that, to reduce active power dissipation in memory, the supply voltage reduction is necessary. Lowering the supply voltage is one of the most straightforward and effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 41–48 Read article