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18 articles for “High-Speed Memory”
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Photonic-Assisted Spintronic Solid-State Switching Model for High-Speed Memory Devices
Abstract: The rapid advancement of high-speed computing and data-centric applications has intensified the demand for energy-efficient and ultra-fast memory technologies. This paper proposes a Photonic-Assisted Spintronic Solid-State Switching Model for next-generation high-speed memory devices. The proposed framework integrates photonic excitation mechanisms with spintronic switching dynamics to enhance data transfer speed, minimize switching delay, and reduce power dissipation in solid-state memory architectures. By combining optical pulse-assisted spin polarization with magnetic tunnel junction-based …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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Review paper on CRUD Operations:Using Arrays , mongoDB for data storage.
Abstract: This project presents a simple implementation of a CRUD (Create, Read, Update, Delete) web application using only arrays for data storage instead of a traditional database. Built with Node.js and Express, the app demonstrates core concepts of data manipulation and RESTful routing. It provides a lightweight framework suitable for educational purposes and early-stage prototyping where database integration is unnecessary. The system handles user- generated posts and operates fully in- memory, …
Published in Journal of Web Engineering & Technology · Vol. 12, Issue 2, 2025 Read article
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Effects of Cluster Computing on Big Data Analysis and Network Topology
Abstract: The rapid expansion of big data has posed substantial difficulties for conventional computing systems. As a result, cluster computing has grown to be a potent method for effective large data processing. Cluster computing involves multiple interconnected nodes functioning as a unified system, pooling together their processing, storage, and memory resources. These nodes are typically connected through high-speed networks such as ethernet or InfiniBand, facilitating efficient data sharing and communication among …
Published in International Journal of Algorithms Design and Analysis Review · Vol. 1, Issue 1, 2023 · pp. 31–39 Read article
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A High Frequency and Power Efficient Memristor Emulator and Its Application
Abstract: This study presents a small, energy-efficient memristor emulator made for use at high frequencies. The proposed circuit has a simple design that only includes three n-type MOSFETs and a grounded capacitor. This means that there is no need for active components or DC biasing. This streamlined architecture not only makes things easier, but it also uses very little power, with dynamic and static power measured at 15.82 μW and 65.6 …
Published in International Journal of Electrical and Communication Engineering Technology · Vol. 3, Issue 2, 2025 · pp. 45–52 Read article
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Comparative Analysis of Modern Programming Paradigms: Evaluating Language Efficiency and Compiler Design Technique
Abstract: This paper attempts to provide some insights into the efficiency of modern programming paradigms via a comparative study and explore the important role played by compiler design in the optimization of these languages. Programming languages have been evolving quickly over time and different paradigms: imperative, functional, or object-oriented programming come with their idiosyncrasies and optimization techniques. The study starts by defining the foundational principles of each paradigm. It then goes …
Published in Recent Trends in Programming languages · Vol. 11, Issue 3, 2024 · pp. 1–9 Read article
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Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Accelerating Unsupervised Feature Learning: Parallelized Training of Denoising Autoencoders
Abstract: Unsupervised representation learning has become a cornerstone of contemporary machine learning, enabling algorithms to extract informative features from un-labelled, high-dimensional data. This work investigates the efficacy of stacked denoising autoencoders (SDAEs) trained via parallelized stochastic gradient descent (SGD) as a scalable approach to feature extraction. By strategically leveraging multi-threaded computation, our study systematically examines the trade-offs between increased parallelism, training efficiency, and the preservation of model accuracy. Experiments on the …
Published in Journal of Image Processing & Pattern Recognition Progress · Vol. 12, Issue 3, 2025 · pp. 56–64 Read article
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Enhancing Data Processing and Storage in Computing Environments: A Survey on the Use of NVMe SSDs
Abstract: In the current era of fast pace technological growth, the efficiency of data processing and storage systems has become a key factor of various computing environments. This survey explores the transformative role of Non-Volatile Memory Express (NVMe) Solid-State Drives (SSDs) across different domains, including Big Data processing, Cloud Computing, High Performance Computing (HPC), and containerized applications. The motivation behind this comprehensive review is to understand how NVMe SSDs, known for …
Published in Recent Trends in Parallel Computing · Vol. 12, Issue 3, 2025 · pp. 01–21 Read article
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A Research Study on Cognitive Health Benefits of Nicotine to the Human Body
Abstract: Background: Nicotine has been primarily known for its addictive properties and associated health risks, particularly in tobacco products. However, recent research has highlighted nicotine’s potential cognitive health benefits, especially in neurodegenerative diseases like Alzheimer’s and Parkinson’s. This study investigates smoking prevalence across mental health conditions, and cognitive impairments in various psychiatric disorders, and explores the possible cognitive health benefits of nicotine. Methods: Data on age and gender distribution, smoking prevalence, …
Published in Research & Reviews: A Journal of Drug Design & Discovery · Vol. 12, Issue 1, 2025 · pp. 16–23 Read article
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CMOS-Based Process-Scalable Analog Circuits for Machine Learning: A Comprehensive Review and Future Directions.
Abstract: Analog computing techniques are gaining attention for machine learning (ML) applications due to their ability to reduce computational complexity. Continuous operations such as addition and subtraction offer a simpler and more efficient approach compared to probabilistic product decoding, which can be sensitive to noise and inconsistent measurements. This paper presents a simulated VLSI implementation of a broadcast edge connection, independent of the MOS component model, along with experimental results. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 8–17 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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Algorithmic Strategies for Complex Data Handling: Optimizing Data Structures for Enhanced Computational Performance
Abstract: We live in an age of big data and processing very large often complicated datasets can be crucial to efficient algorithmic performance. This paper discusses different algorithmic techniques when working with difficult data and how to arrange your information structures correctly for better functionality in large-scale methods. It checks the impact of different algorithms like sorting, searching, and hashing in boosting its processing speed as well as memory use. This …
Published in International Journal of Data Structure Studies · Vol. 2, Issue 2, 2024 · pp. 1–10 Read article
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Advancements and Challenges in Computer Hardware Technology Management: Innovations, Performance, and Future Directions
Abstract: Modern computing systems depend on computer hardware technology for performance, efficiency, and innovation. Processing units, memory storage, input/output devices, and networking hardware are covered in this article. It emphasizes how multi-core processors, SSDs, and integrated circuits have increased computational power and speed. The essay also discusses quantum computing, edge computing, and the IoT, which will change hardware. Finally, the essay discusses hardware design challenges such power consumption, heat control, and …
Published in International Journal of Solid State Innovations & Research · Vol. 3, Issue 1, 2025 · pp. 1–8 Read article
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Automating Compiler Optimization: A Machine Learning Approach
Abstract: This study reports on an ML-based approach to compiler optimization, complementing traditional optimization methods that rely strongly on hand-tuned settings. Compiler optimization plays a key role in performance-speedup and energy optimization of complex contemporary software systems. However, the traditional approach to optimizer settings involves laborious, error-prone, and scale-insensitive human-in-the-loop intervention, especially in the complex and high-demand environments in which today's computing application thrives. By integrating RL and GA, we can …
Published in Journal of Artificial Intelligence Research & Advances · Vol. 12, Issue 1, 2025 · pp. 12–16 Read article
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Ferroelectric Materials for Next-Generation Non-Volatile Memory Applications
Abstract: The continuous scaling of conventional memory technologies is increasingly constrained by limitations in power consumption, speed, endurance, and integration density. As data-intensive applications such as artificial intelligence, Internet of Things, and edge computing demand fast and energy-efficient memory solutions, alternative non-volatile memory technologies have gained significant attention. Ferroelectric materials, characterized by their reversible spontaneous polarization, offer a promising pathway toward next-generation non-volatile memory due to their intrinsic non-volatility, low operating …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 1–9 Read article
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Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed
Abstract: This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 1–13 Read article