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5 articles for “Embedded DSP”
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Machine Learning–Guided Cognitive RF System with Dynamic FFT Resolution and Multiplier Reconfiguration for Adaptive Anti-Jamming Communication
Abstract: This paper presents a hierarchical adaptive RF communication system that integrates signal quality-based pre- processing with machine learning-driven signal classification to achieve robust and resource-efficient operation in dynamic, interference-prone environments. Unlike prior art that addresses adaptive RF, ML classification, or anti-jamming individually, this work uniquely combines real-time SNR/RSSI-based signal strength estimation with dynamic FFT size selection (64-, 256- , or 512-point) and arithmetic-level multiplier reconfiguration (CORDIC, Distributed Arithmetic, and hybrid …
Published in International Journal of Radio Frequency Innovations · Vol. 4, Issue 1, 2026 Read article
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Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics
Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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Graphene–Perovskite Hybrid Opto-Electronic Modulators for Ultra-Low Power Optical Communication
Abstract: This paper proposes a novel self-adaptive neuromorphic opto-electronic transceiver architecture designed to enhance the intelligence, adaptability, and efficiency of next-generation optical communication networks. The proposed system integrates neuromorphic computing principles with photonic signal processing to enable real-time learning, dynamic resource allocation, and autonomous compensation of channel impairments such as dispersion, nonlinearities, and noise. Unlike conventional transceivers, the developed model employs spiking neural networks embedded within opto-electronic circuits to mimic biological …
Published in Trends in Opto-electro & Optical Communication · Vol. 16, Issue 1, 2026 · pp. 41–52 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article