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11 articles for “CMOS logic structures”
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Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology
Abstract: Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 17–23 Read article
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Ultra Low-Power 9-Transistor Flip-Flop Design
Abstract: AbstractThe use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate. The challenge for VLSI technology is mainly in leakage power consumption. Flip-Flops (FFs) are the basic storage elements used extensively in digital system designs. It accounts for 20%–45% of the total system power and may considerably impact the chip area. In this paper, an ultra-low-power true …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 27–32 Read article
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Investigation of Pass Transistor Logic and CMOS Logic Configuration Based D-Multiplexers
Abstract: Pass Transistor Logic (PTL) arrangement depicts a few rationale families utilized in the plan of incorporated circuits. It lessens the include of transistors utilized making distinctive rationale entryways, by killing excess transistors. The pass transistor is driven by an intermittent clock flag and goes about as an entrance change to ON (1) or OFF (0), contingent upon the information flag. The utilization of pass transistor rationale has brought about noteworthy …
Published in Journal of Microelectronics and Solid State Devices · Vol. 9, Issue 2, 2022 · pp. 1–8 Read article
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems
Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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Design of High-Speed and Low-Power Carry Skip Adder
Abstract: In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 35–44 Read article
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Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article
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Multi-Sensor System for Underwater Pothole Detection to Enhance Road Safety During Monsoon Seasons
Abstract: Monsoon seasons across India and similar tropical regions severely compromise road safety by causing water accumulation that conceals dangerous potholes beneath stagnant pools, leading to frequent vehicle damage, tire punctures, and fatal accidents. Traditional detection methods relying on smartphone accelerometers, ultrasonic sensors, or machine vision fail under flooded conditions due to acoustic signal reflection at water surfaces and optical distortions from glare and turbidity. This research proposes an innovative multi-sensor …
Published in International Journal of Mechanical Dynamics and Systems Analysis · Vol. 4, Issue 1, 2026 · pp. 25–32 Read article