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193 articles for “transistor”
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Signal Integrity Analysis of Single Walled Carbon Nano Tube based Interconnects at 32 nm Technology Node
Abstract: The rising demands for ultra-high-speed processors and portable devices have made the transistor and interconnect scaling a challenging issue in present days. In this work, the impedance parameter of copper and CNT based interconnects are calculated at 32 nm technology node for different lengths. The performances of CNT based interconnects are analyzed and compared with Cu based interconnects in terms of crosstalk. The conventional copper interconnects are not able to …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 33–42 Read article
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Electrical Characteristics of AlGaN/GaN/AlGaN HEMTs
Abstract: AbstractA maximum drain current of 556 mA is achieved by the simulated structures of double-heterojunction AlGaN/GaN/AlGaN high electron mobility transistors (HEMTs) using the SILVACO-ATLAS software tool in this work. The drain current is observed as higher at shorter gate length. The drain current is found as higher at larger aluminium mole fraction. Also, the drain current is found as higher at larger thickness of AlGaN barrier layer. The drain current …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 7–17 Read article
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Simulation Studies on the Drain Characteristics of Microelectronic AlGaN/GaN HEMTs Corresponding to the 30 nm of AlGaN Nano-Layer
Abstract: AbstractIn this work, the simulation studies are performed on high electron mobility transistor (HEMT) structures using the SILVACO-ATLAS software tool. The drain characteristics of HEMT structures is investigated with respect to the Aluminium mole fraction, drain voltage, gate voltage, and gate length at 30 nm thickness of AlGaN nano-layer. The simulation studies on the effect of gate length to control the drain characteristics are a novelty of this work. The …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 1, 2017 · pp. 8–16 Read article
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A Double-Ended Read-Decoupled 8T SRAM Cell with Improved Read Stability and Access Time at 45 nm Technology
Abstract: AbstractDue to rampant leveling of instrument measurements, the stability of an SRAM cell is the biggest anxiety for upcoming technology. In this paper, it is introduced by an 8T (8-transistor) SRAM cell. The enlarged data stability is offered by proposed cell until read operation. The voltage scale of the node keeping ‘0’ is enlarged by introduced cell and thus it achieves a near butterfly curve that is vital to creation …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 2, 2017 · pp. 29–33 Read article
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Design of a Multipurpose Ternary Arithmetic Circuit Using CNTFET
Abstract: AbstractIn this paper, a multipurpose ternary arithmetic circuit is presented for ternary processors based on carbon nanotube field effect transistors (CNTFETs). Both addition and subtraction can be performed using same circuit’s configuration, which is the special feature of the proposed circuit. The combination of pseudo and complimentary logic structure are employed to blend the binary and ternary logic techniques. The propagation delay and power delay product are 139.5 pico second …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 13–24 Read article
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Simulation Studies on the Electrical Characteristics of Novel Nanoelectronic AlGaN/GaN/AlGaN Double-Heterojunction HEMTs for Industrial Applications
Abstract: AbstractWe report the drain characteristics of AlGaN/GaN/AlGaN double heterojunction (DH) high electron mobility transistors (HEMTs) with the associated quantum well depths. The drain current is higher corresponding to the larger doping concentration of AlGaN nano-layer. The drain current is higher with the larger gate voltage at any particular drain voltage. The quantum well depth is significantly higher with the increasing doping concentration of AlGaN nano-layer. About the novelty of this …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 3, 2016 · pp. 6–18 Read article
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Variations of Source Current in the Double-Heterojunction HEMTs
Abstract: AbstractIn this report, we have studied the variations in source current with respect to drain voltage corresponding to the double heterojunction (DH) high electron mobility transistors (HEMTs). Also, the effects of gate voltage and aluminium mole fractions on source current are studied. In this work, the highest source current achieved is 3.3 mA. This work may be useful to design many nanoelectronic HEMTs.Keywords: Source current, drain voltage, gate voltage, mole …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 3, 2016 · pp. 19–24 Read article
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Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design
Abstract: Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 15–20 Read article
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Recent Development in Ga2O3 MOSFETs for High Power RF Applications
Abstract: Abstract: This paper attempts to investigate the property of recently reported gallium oxide as a high power RF device by studying its related high power RF characteristics, and suggest a path to develop metal-oxide-semiconductor field effect transistor (MOSFET). Keywords: MOSFETs, Wide Band Gap Semiconductors, Gallium Oxide and RF ICsCite this ArticleNarendra Yadava, R.K Chauhan. Recent Development in Ga2O3 MOSFETs for High Power RF Applications. Journal of Semiconductor Devices and Circuits …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 21–25 Read article
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Performance Analysis of Fully Flexible Organic Humidity Sensor with Top-Contact and Bottom-Contact OTFTs
Abstract: Abstract: Organic field-effect transistor (OFET) based humidity sensors are extensively used nowadays due to their low cost, mechanically flexible and compatibility with lower temperature fabrication techniques that support the plastic substrate based device and circuit applications. This paper investigates the humidity dependence of performance of organic humidity sensor with Top-Contact and Bottom-Contact OTFTs. Subsequently, impact of channel length on sensor performance is analyzed. The humidity sensitivity of organic sensor drain …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 26–34 Read article
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Analysis of Operational Transconductance Amplifier using Low Power Techniques
Abstract: The paper presents a low power design of Current Mirror based Operational Transconductance Amplifier. The analysis of operational transconductance amplifier has been carried out using conventional gate-driven and low power techniques realised with quasi-floating gate, bulk-driven and bulk-driven quasi-floating gate transistors. The comparative analysis of performances of the amplifiers designed using the above techniques indicate that the best performance is achieved by bulk-driven quasi-floating gate approach. Using bulk as input, …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 14–22 Read article
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Design and Simulation of Ternary Gates Using Fin-FET
Abstract: In recent years, digital communication system has becomes more popular. But the on-chip interconnections have become a major problem as more and more modules are packed into a chip by reducing the gate size. As the gate size is reduced further the complexities in the circuit increases. Binary logic circuit dissipates a lot of energy, increase processing time, and causes coupling effect. In the Ternary logic system, there are three …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 4–18 Read article
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Design and Performance of Semiconductor-Biosensor
Abstract: In this work, a high electron mobility transistor (HEMT) based biosensor is designed to detect the virus-protein. In this work, all the simulation-studies are carried out in the SILVACO-ATLAS physical simulator using the following models: Shockley Read Hall (SRH), band gap narrowing, Auger recombination, and Fermi Dirac statistics. Newton trap numerical solver is used in the device simulation. Conduction band engineering of the biosensor is studied. DC and RF properties …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 2, 2021 · pp. 1–13 Read article
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Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET
Abstract: We carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k.Based on device simulation we find that the asymmetric oxide shows …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 2, 2021 · pp. 14–20 Read article
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AMBA 3 AHB Lite Protocol design and verification
Abstract: As technology progresses, the amount of logic and transistors that can be packed on a device that runs an extreme integrated SoC design grows. The most significant feature of a SoC is its connectivity. In most SoCs, the AMBA (Advanced Microcontroller Bus Design) bus is the most often used on-chip bus design.AMBA was first introduced by ARM. The AMBA AHB-Lite synthesizable design meets the requirements of high-performance synthesizable designs. Because …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 3, 2021 · pp. 47–55 Read article
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Design and Implementation of Array for Scaling Power and Area in 4t SRAM Cell
Abstract: In this article in order to reduce the power and area of the Static Random-Access Memory (SRAM) array while maintaining the competitive performance. By using the CMOS technology, the design structure is made to for desired configuration of SRAM array by utilizing the SRAM cell and six-transistor (6T), In order to reduce the number of switches for enhancing performance working with the deep submicron of values 130nm, 90nm and 65nm …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 29–33 Read article
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DC and RF Analysis on Specific Quantum-Well Heterostructures
Abstract: Polarization-graded AlGaN back-barrier nano-layer is introduced in high electron mobility transistor (HEMT) structure to have an improved drain current characteristics and better radio-frequency performance, using two-dimensional drift-diffusion simulation by SILVACO-ATLAS physical simulator. In this work, the AlGaN/AlN/GaN/AlGaN/GaN double heterojunction HEMT structure is optimised with graded back barrier layer to study the DC and RF performances. Investigation of this structure with graded back barrier layer is the novelty of this work. …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 1–13 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology
Abstract: A low Off-Set high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18µm …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 21–27 Read article
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Designing of GaAs Based Resonant Tunneling Diode and Nano Scale Applications with Considering NEGF
Abstract: Present situation of eletronic area in the world required small devices as well as low power dissipation and ultra high speed application. At this moment the presence of resonant tunneling diode can over come this type of problem and take a big role in nanoscale digital and analog applications.In this researh article is to demonestrated effect of asymmetric barrier with respect to symmetric barrier and digital inverter and THz analog …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 1–18 Read article