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1205 articles for “over speeding”
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Abstract: A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 38–41 Read article
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers
Abstract: VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 32–36 Read article
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Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology
Abstract: Paper describes the performance analysis, implementation and characterization of low-power and high-speed shared charge clocked-latch based comparator using 90-nm technology. There are two different topologies of the comparator viz. impedance dividing and differential current sensing comparators are combined to take the advantages and use their good features. The main focus of design is on improvement in speed by sharing charge and reduction in power dissipation. The topology is implemented in …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 20–26 Read article
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Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime
Abstract: In this paper, performance of the VLSI circuits designed with strained silicon MOSFETs is analysed andcompared with bulk MOSFET. Emphasis is being given on the evaluation of speed, power and noisecharacteristics. An inverter circuit designed with single channel and dual channel biaxial strained MOSFETsof 40 nm channel length and 0.3 germanium mole-fraction is being taken to evaluate the performance throughsimulation. The device design and circuit simulation is done in Sentaurus …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 15–20 Read article
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Design and RTL Implementation for AHB-APB Bridge on SoC
Abstract: The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 44–52 Read article
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Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture
Abstract: Content Addressable Memory (CAM) is a storage unit used for faster accessing of lookup table that reduces processing time for search operation. It is mainly used very-high-speed searching applications like computer networking devices. The MAC address table is implemented with a CAM so that the destination port can be easily detected by reducing the switch’s latency. CAM gets its high speed of operation by parallel search mechanism. This paper proposes …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 29–34 Read article
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An Overview to Transmitter Device Or Gesture Device Components
Abstract: An accelerometer is an electromechanical scheme used to measure acceleration forces. Those powers may be stationary, like the nonstop force of gravity or, as is the case with many movable devices, dynamic to intellect program or vibrations. Acceleration is the capacity of the modification in velocity, or speed separated by phase. Let us take an example, a car speed up from a halt to 60 mph in six seconds is …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 3, 2019 · pp. 12–15 Read article
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Hardware Implementation of Discrete /Inverse Discrete Cosine Transform Using Redundant Number System CORDIC Processors
Abstract: Rapid enhancement in multimedia service running on portable application has forced the development of high quality and low power implementation of complex signal processing algorithms. Image and video processing are typical application of multimedia system. Image compression and decompression using DCT/IDCT are the two algorithms commonly used in MPEG standard of image processing. For an image of N x N size, DCT/IDCT would require N4 multiplications and increases complexity. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 1, 2021 · pp. 35–42 Read article
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article
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Reduce the Leakage Current and Power in VLSI Technology
Abstract: Demand for portability Reduce and increase in size, low cost, low dynamic power, low leakage current, low sub threshold current, and the necessity to minimise at least one of these. Circuit complexity increases with circuit integration. Memory and microprocessors are included in mass-produced chips. Microcomputer systems central system memory uses dynamic random-access memory (DRAM). One benefit of DRAM memory is its high speed and capacity integration. The examination of DRAM …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 3, 2023 · pp. 19–25 Read article
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A Review on Sybil and Sinkhole of Service Attack in VANET
Abstract: AbstractVehicular Ad-hoc Network (VANET) is one of the forms of wireless network. VANET communication is between vehicle to vehicle and vehicle to infrastructure. Vehicular Communication (VC) systems of a practical dealing signal. The safety and security are major issues to secure our network. It prevents critical information from arriving. It also increases the danger to the driver, if it has to depend on the application’s information. For example, malicious node …
Published in Recent Trends in Electronics Communication Systems · Vol. 5, Issue 1, 2018 · pp. 7–11 Read article
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Effect of Internal Heat Generation on the Onset of Rayleigh-Bѐnard Chandrashekar Convection in a Micropolar Fluid with Maxwell Cattàneo Law
Abstract: AbstractThe effect of result from the substitution of the classical Fourier law by the nonclassical Maxwell-Cattàneo law and influence of internal heat generation on the Rayleigh-Bѐnard Chandrashekar internal heat generation parameter has a significant impact on the thermal mode making the system unstable. The eigen value is obtained for free-free, rigid-free and rigid-rigid velocity boundary combinations with isothermal temperature on the spin-vanishing boundaries. The influence of various micropolar fluid parameters …
Published in Recent Trends in Fluid Mechanics · Vol. 5, Issue 1, 2018 · pp. 31–43 Read article
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Effect of Throughflow on the Onset of Electro-Thermo Convection in a Micropolar Fluid with Maxwell-Cattaneo Law
Abstract: AbstractThe effect of throughflow on the onset of Electro-thermo convection in a micropolar fluid with Maxwell-Cattaneo law is studied using the linear theory. The eigenvalue is obtained for free-free, rigid-rigid and rigid-free velocity boundary combinations with isothermal and adiabatic on the spin-vanishing boundaries using galerkin technique. The influence of Peclet number, Electric Rayleigh number and various micropolar fluid parameters on the onset of convection has been analyzed. It is found …
Published in Recent Trends in Fluid Mechanics · Vol. 5, Issue 1, 2018 · pp. 1–17 Read article
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Short Review on the Effects of Plasma Processing Techniques in PMMA Microfluidic Device
Abstract: Abstract: The plasma processing techniques are useful for surface modifications on polymer surfaces. The appropriate surface modification alters the level of static contact angles on the polymer surfaces. The surface-driven microfluidic flow of suitable working liquid is sensitive to the static contact angle of microchannel surfaces fabricated by different polymers. Therefore, plasma processing techniques are suitable to vary the flow speed of working liquids in microfluidics. In future, this review …
Published in Recent Trends in Fluid Mechanics · Vol. 6, Issue 1, 2019 · pp. 20–22 Read article
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Underwater Wireless Communication Using Visible Light
Abstract: The proposed method leads to a data communication architecture that transmits audio through water using visible light. This model uses a PIC microcontroller as hardware. The transmitter is a laser, while the receiver is a photodiode receiver. Today, high-speed wireless communications are required for many commercial, research and subsea applications. Current underwater communication methods, such as acoustic communication, suffer from significant delay and poor data quality, while underwater radio communication …
Published in Recent Trends in Fluid Mechanics · Vol. 10, Issue 3, 2023 · pp. 19–26 Read article
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Modeling of The DFIG Wind Turbine
Abstract: This paper studies the power-speed characteristics and the fundamentals of wind electrical systems along with the modeling of the various wind turbine structures and simulation of the same using MATLAB-SIMULINK. It deals with the vector control and modeling of the Doubly-Fed Induction Generator (DFIG), which can maintain the DC link voltage. This paper focuses on the analysis of traditional decoupled d-q vector control approaches for control of DFIG wind turbines. …
Published in Trends in Electrical Engineering · Vol. 5, Issue 3, 2015 · pp. 114–118 Read article