Hardware Implementation of Discrete /Inverse Discrete Cosine Transform Using Redundant Number System CORDIC Processors

jayashri mallappa Rudagi

Abstract

Rapid enhancement in multimedia service running on portable application has forced the development of high quality and low power implementation of complex signal processing algorithms. Image and video processing are typical application of multimedia system. Image compression and decompression using DCT/IDCT are the two algorithms commonly used in MPEG standard of image processing. For an image of N x N size, DCT/IDCT would require N4 multiplications and increases complexity. To reduce the complexity and increase the speed many algorithms have been proposed. This paper presents the implementation of DCT/IDCT using radix-2, radix-4 and radix-8 CORDIC processors and comparison with Loeffler Algorithm. The implementation of high radices results into reduction in the computations thus making it faster and power efficient. By using higher radix CORDIC processor 50% advantage for speed enhancement and 80% power reduction have been observed, respectively. The results also indicate that radix-8 CORDIC Processor implementing DCT/IDCT (CRDCT/IDCT) in comparison with CRDCT/IDCT using radix-2 and radix-4 yields reduction in critical path delay by 47% and 28% with a sacrifice on area in terms of more hardware by 12% and 30% respectively.