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34 articles for “power delay product”
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 42–54 Read article
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Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element
Abstract: Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge frequencies. To lower its latency, the C-element has additionally …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 36–44 Read article
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article
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Implementation and Analysis of Full Adder using low Power Adiabatic Techniques
Abstract: AbstractIn this study, authors have discussed, designed and compared the low power adiabatic logic energy efficient recovery logic (ECRL) and positive feedback of adiabatic logic (PFAL) with conventional Complementary Mosfet (CMOS) logic. A one-bit full adder using these design techniques are implemented and results are compared like power, delay, transistor count and power delay product. Tanner tool v13 is used for designing of schematic and simulation. From the result, it …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 1–8 Read article
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Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power
Abstract: This paper presents the analysis and characterization of various topologies of dynamic latch based complementary metal oxide semiconductor (CMOS) comparator. Various comparator topologies like resistor divider comparator (RDC), differential pair comparator (DPC), double-tail dynamic latched comparator (DTDLC), energy efficient two-stage comparator (ETWC) and two-stage dynamic comparator (TSDL) are analyzed and compared for various performance parameters. Besides zero static power consumption, resistor divider comparator has high offset voltage and it depends …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 86–98 Read article
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Different Compressor Adders
Abstract: AbstractMultipliers are one of the main blocks which decide the circuit performance as well as computation speed. In multiplication, addition of partial products contributes most to the circuit delay, power, and area. In this project, compressor adders are used to reduce this delay. Hence, compressors are a major part of the multiplier circuit that decides the overall speed of the system. For high-speed processing and higher systems, a huge number …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 19–26 Read article
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Comparative Analysis of Partial Product Addition in Vedic Urdhva Tiryakbhyam Multiplier
Abstract: Multiplication is one of important operations performed in many digital signal processing applications. Hence the performance of the multiplier will affect the overall performance of the DSP processor. The methods like booth multiplier, and array multiplier are used. Vedic multiplication technique had proved its importance in getting the speed of multiplication. It is required to add the generated partial products quickly, to generate the result of multiplication faster. To add …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 15–32 Read article
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Ranking of Relative Importance of Productivity Factors in Indian Construction Projects
Abstract: Productivity remains an intriguing subject and a dominant issue in the construction sector. Best performance is unachievable with poor productivity resulting in time over-run and consequently cost escalation of projects. Hence, productivity is of critical importance to the profitability of most construction projects and it is essential that attempts to be made to improve productivity. Any improvement in productivity cannot be achieved without understanding the factors that adversely affect productivity. …
Published in Journal of Construction Engineering, Technology & Management · Vol. 7, Issue 1, 2017 · pp. 67–77 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Digital Front-End Architecture of ECG Acquisition System with 0.5V Supply
Abstract: AbstractDue to the popularity of portable electronic products, low power systems have attracted more attention in recent years. Dynamic power consumption remains to be the biggest contributor to the total power consumption of a hardware design. A new power efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area has been proposed in this paper. The design of analog-to-digital converters (ADCs) is …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 2, 2016 · pp. 11–20 Read article
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Experimental Investigation on 4-Stroke Diesel Engine Using Waste Cooking Oil Biodiesel Fuel
Abstract: Due to using of fossil fuels, the world today is faced with serious environmental pollution. However, these fuels are limited and depleting day by day as the consumption is increasing very rapidly. Hence, it is necessary to find out a clean alternative fuel produced from renewable sources. Biodiesel production and applications are gaining popularity in recent times due to diminishing petroleum reserves and detrimental environmental impacts. Edible and non-edible oils …
Published in Journal of Automobile Engineering and Applications · Vol. 2, Issue 2, 2015 · pp. 19–28 Read article
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Study of 5G Technology and its impacts - Review
Abstract: Digitization is an ongoing revolution in the manufacturing industry. 5G technology is expected to play an important role in providing connectivity. Digitized factories place high demands on technical availability and therefore also on maintenance performance. However, it is difficult to incentivize senior decision makers to invest in maintenance, as impacts are often delayed and difficult to verify upstream. To quantify long-term effects, discrete event simulation (DES) has been identified as …
Published in Recent Trends in Electronics Communication Systems · Vol. 8, Issue 3, 2021 · pp. 40–50 Read article
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Utilizing Artificial Intelligence and Remote Sensing to Predict Flooding in Real-Time and Address Climate Resilience Policy in South Asia
Abstract: South Asia, a region characterized by hydro-climatic instability, faces an intensifying risk from devastating flooding, aggravated by human-induced climate change and intricate river basin interactions. Traditional flood prediction systems, based on limited in-situ data and resource-intensive physical models, have serious delays and resolution problems that make it harder to reduce disaster risk. The combined applications of Artificial Intelligence (AI) and high-resolution remote sensing (RS) constitute a paradigm shift in real-time …
Published in Journal of Remote Sensing & GIS · Vol. 17, Issue 1, 2026 Read article