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85 articles for “Clock”
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Implementation and Verification of Dual Port RAM for High-speed Applications
Abstract: It is important to have an appropriate medium for transmitting data among parallel running processes in multi-processor-based applications. Multi-processor systems are used to handle complex tasks that require a lot of processing power, and they rely on parallel running processes to achieve this. However, one of the major limitations of these systems is the slow transmission of data among parallel running processes. This is due to the fact that in …
Published in Journal of Electronic Design Technology · Vol. 14, Issue 2, 2023 · pp. 37–41 Read article
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Automatic Time Scheduler/College Bell System
Abstract: AbstractThe world over the decades has made considerable advancement in automation; automation is employed in every sector whether it is home or industry. Here, a new and inexpensive design is being presented. This design project finds application in educational institutions at all levels that have multiple sessions of teaching and prerequisite breaks for the students. The benefit of the design is that the bell trinkets at the beginning of each …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 10–15 Read article
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Low-Voltage Low-Power Single Supply Rail-to-Rail High Resolution Comparator in 0.18 µm CMOS Technology
Abstract: This paper presents an absolute input rail-to-rail ultrahigh-resolution comparator for low-voltage low-power applications. To enhance the input range rail-to-rail, the proposed comparator utilizes dynamic configuration with a MOSFET-only clock booster to supply a boosted voltage for pre-amplifier stage. Cadence SPICE simulations of the proposed comparator in a 0.18 μm CMOS process confirm the rail-to-rail input range with a supply voltage of 1.2 V with a decision time less than 9 …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 87–91 Read article
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A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit
Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article
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Arduino Based Smart Bell
Abstract: In today’s era, many school/college bells are operated manually. But there is requirement of accuracy in operation. In schools/colleges, there are many digital clocks available with bells but they ring only at specific time and cannot stop after specific time. Here a new and inexpensive design is being presented. The Arduino uno is used for controlling all the functions, it gets the time through the keypad and stores it in …
Published in Trends in Electrical Engineering · Vol. 9, Issue 1, 2019 · pp. 36–40 Read article
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Enhanced RANO Protocol by Reduced Packet Loss in Wireless Sensor Networks
Abstract: In wireless sensor network (WSN) a lot of sensed data and routing information has to be sent which often have some time constraints so that the information can be utilized before any mishap occurs. The time synchronization makes accessible the avoidance to collision and better safety to the nodes. A variety of category criteria are formed to grant time synchronization—NTP incident, GPS symmetric analysis. The problems are lack of energy …
Published in Recent Trends in Sensor Research & Technology · Vol. 3, Issue 1, 2016 · pp. 1–9 Read article
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Light-Dark Cycle Disruption in Hypothalamus Tissue of Mus Musculus Causes Change in the Expression of Gm45928 Gene
Abstract: The majority of organisms on earth display consistent 24-hour rhythms in their physiology and behavior due to circadian biology. Light and dark cycles play a key role in setting our internal body clock, which controls things like our sleep patterns, hormone levels, body temperature, and metabolism. The disruption of the light-dark cycle has significant effects on the molecular and behavioral rhythms of the circadian clock of hypothalamus. Gm45928 is a …
Published in International Journal of Cell Biology and Cellular Functions · Vol. 3, Issue 1, 2025 · pp. 32–46 Read article
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Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits
Abstract: This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 · pp. 30–42 Read article
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Ultra Low-Power 9-Transistor Flip-Flop Design
Abstract: AbstractThe use of very large scale integration technology in high performance computing, wireless communication, consumer electronics has been rising at a very fast rate. The challenge for VLSI technology is mainly in leakage power consumption. Flip-Flops (FFs) are the basic storage elements used extensively in digital system designs. It accounts for 20%–45% of the total system power and may considerably impact the chip area. In this paper, an ultra-low-power true …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 27–32 Read article
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Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology
Abstract: Analog technique with feedback loop is applied to correct the duty cycle of any circuit without using more power. Pulse width modification is used to vary the duty cycle of clock signal. PMC cell is designed for expansion and contraction of pulse width. Differential amplifier based filter is used to detect the duty cycle of the particular clock signal. Differential amplifier and OpAmp are used to achieve adequate gain. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 13–22 Read article
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A Review on Charge Pump Circuits for PLL Applications
Abstract: This paper presents a review on various architectures of charge pumps (CP) for high speed Phase-locked loop (PLL) applications. The different nonlinear marvels that influence the execution of PLL in view of the CPs circuit are examined. The various high performance CP circuits with reference voltage source, reference current source are analyzed that reduces the problems associated with the traditional charge pump circuit that consists leakage current, clock feed-through, charge …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 1–11 Read article
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Study and Analysis of Delay Faults of Embedded Processor using Dynamic Voltage Scaling Methods
Abstract: Voltage over-scaling has been a possibility for energy dependability compromise. This research will look into its effectiveness and the potential for rationale deferral flaws. Our contextual investigation on an ARM Cortex-M0 processor with business 45 nm libraries shows that the quantity of defer deficiencies increments decisively after the principal bombing working point which infers that voltage overscaling will be wasteful after the basic working point. This recommends the need of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 1, 2022 · pp. 15–19 Read article
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Architectural Evolution of RISC Processors: From Early Research Prototypes to Modern Industrial Implementations
Abstract: This paper surveys the architectural evolution of Reduced Instruction Set Computer (RISC) architectures from early research prototypes to modern industrial processors, tracing four decades of design refinement across academic, embedded, server, mobile, and open- hardware ecosystems. Core ISA principles, pipeline evolution, compiler–hardware co-design, and quantitative performance modeling are analyzed through four representative industrial implementations: MIPS 74K, SPARC T4, ARM Cortex-A72, and SiFive U74 (RISC-V). Each processor is examined in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 29–39 Read article
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Power Consumption Reduction using Microarchitecture Techniques for Modern Multicore Microprocessors
Abstract: The development in the semiconductor technology is helping the designer to make the systems as compact as possible. We are moving towards 14 nm fabrication technology. The technology scaling is going much down but it is also the reason to bring several crucial issues on the surface which is very difficult to handle. The various advance processor architecture design concepts helped in increasing speed by keeping the power consumption under …
Published in Current Trends in Information Technology · Vol. 3, Issue 3, 2013 · pp. 16–20 Read article
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Role of Facility Management in Fire and Life Safety in Hospitals
Abstract: Hospitals are significant buildings where people receive medical care around-the-clock. An internal hazard like a fire is more disruptive and puts more pressure on hospital authorities to ensure the safety of the patients and visitors who are unfamiliar building and the procedures to follow in case of a fire. In order to keep the patients safe in the event of a fire, every healthcare facility needs to have a plan …
Published in International Journal of Architectural Design and Planning · pp. 8–17 Read article
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High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Abstract: This paper focuses on the design and optimization of latch comparators for high-speed data converter applications. The performance of different comparator architectures is compared in terms of speed, power consumption, and noise performance. The proposed latch comparator architecture uses a preamplifier to boost gain and sensitivity, and a latch to store the output signal. The latch comparator design is optimized for low power consumption and high speed, and is implemented …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 23–32 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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Artificial Machine Intelligence Language for Banking Chatbot
Abstract: The developed system introduces a banking chatbot utilizing Artificial Intelligence Markup Language (AIML) to enhance customer interactions within the banking sector. With the increasing demand for efficient customer service and the adoption of automated systems, chatbots have emerged as a pivotal solution for banks to streamline operations and improve user experience. The proposed banking chatbot leverages state-of-the-art natural language processing (NLP) algorithms powered by AIML to interpret user queries, provide …
Published in Journal of Communication Engineering & Systems · Vol. 14, Issue 3, 2024 · pp. 8–13 Read article
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RTL to GDSII Implementation UART using Verilog and Cadence tools
Abstract: The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 1–7 Read article
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Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element
Abstract: Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge frequencies. To lower its latency, the C-element has additionally …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 36–44 Read article