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283 articles for “Semiconducting”
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FPGA Implementation of LDPC Codes
Abstract: AbstractLow Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 21–28 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Review Paper To Design a Low Power CNTFET Based XOR Gate
Abstract: The continuous scaling down of Silicon technology leads to various critical challenges and reliability issues such as short channel effect, high leakage current, interconnect problems, etc. CNTFET is the most probable substitutes to traditional MOSFET. The CNTFET device based circuits portray advantages with its better control over the device channel, reduced leakage current, reduced short channel effects. The CNTFET based XOR gate circuits incur the minimum power and energy dissipation. …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 48–53 Read article
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A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network
Abstract: Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately, solve the communication problem, and to obtain high-performance integrated circuits. In this study, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to fulfill the requirements of silicon-based ICs must satisfy to successfully perform copper electrical interconnects (IEs). Keywords: Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonicsCite this ArticleAbhishek Sharma, Sudhir Kumar …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 36–44 Read article
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Characterization of Low Power-Low Jitter Digital PLL
Abstract: The architecture design is being done in transistor level and tool which supports transistor level design. Mentor Graphics Tool is used for transistor level design and its simulation design. There are few tools which support design simulation like HSpice, Spectre and PSpice. Also a foundry support is from Taiwan Semiconductor Manufacturing Corporation (TSMC) (i.e.) technology model files 180 nm from TSMC for simulation. This article presents design for 1.5 GHz …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 23–32 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Design and Implementation of Low Noise Amplifier using 90 nm MOS Technology for Bluetooth
Abstract: In the era of Miniaturization it is necessary that analog field develops at par with the digital world. To design RF circuit on the single chip it is necessary that noise performance of active semiconductor devices are studied and configure the devices in such a way that noise gets minimized. In this paper various kinds of noise in the devices are explained at a brief. Low Noise Amplifier for Bluetooth …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 13–19 Read article
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Power Reduction at 90 nm through Circuit Level Modification
Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article
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Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power
Abstract: This paper presents the analysis and characterization of various topologies of dynamic latch based complementary metal oxide semiconductor (CMOS) comparator. Various comparator topologies like resistor divider comparator (RDC), differential pair comparator (DPC), double-tail dynamic latched comparator (DTDLC), energy efficient two-stage comparator (ETWC) and two-stage dynamic comparator (TSDL) are analyzed and compared for various performance parameters. Besides zero static power consumption, resistor divider comparator has high offset voltage and it depends …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 86–98 Read article
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Challenges Beyond 100 nm MOS Devices
Abstract: MOS devices have been aggressively scaled down in research and in the production in last few years. Sub-100 nm feature size MOS circuits have been used for many. However, many serious limitations and problems emerged with such a small geometry MOSFETs are used to realize very large-scale integrated circuits. Commercial 45 nm technology node, has much higher production cost and it is one of the greatest concern for scaling down …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 1–4 Read article
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Layout Design, Fabrication and Characterization of n-Channel MOSFET
Abstract: Primary force behind evolution of semiconductor industry is MOSFET, after its first IC based experimental demonstration in 1960s. It is fundamental working unit of most of the electronic circuits like cells in living being. Number of devices on a single chip has been increased with rapid phase with evolution of new technology of materials. Today there are more than 4 billion transistors are there on a single chip with effective …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 13–18 Read article
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Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Abstract: This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 53–61 Read article
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Survey of System-on-Chip Modular Test Approach
Abstract: The advancement in semiconductor technology over the past few decades has enabled the industry to develop new design and reuse methodologies referred as System-on-chip (SoC) design. These typically integrate heterogeneous mix of various complex analog and digital cores, with all their necessary electronic circuitry. The recent advancements have led to the use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance, minimum average interconnect length, reduced …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 56–70 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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Design of CMOS AM Modem for Wireless Sensors
Abstract: A design of amplitude modulated (AM) modem, compatible to CMOS technology for its monolithic integration with either wireless microsensors or other sources of baseband signals, is presented in this paper operating in different frequency bands. Circuits functional in different operating conditions are considered in the paper to satisfy the requirement from low- to high-speed signals produced either from the wireless sensor or other signal source to be modulated on a …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 44–51 Read article
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Simulation of Three Section Multilevel Inverter with Reduced Range of Switches
Abstract: Because of high generation development, the demand and excellent of electric strength ishigher than earlier than. Furthermore, due to the advancement of semiconductor, thespecification of electricity devices and strength conversion method turn out to be stricter. Oneof the energy converters that may remodel DC to AC is called inverter. An inverter is the intermedium to transmit the electricity to other electric device such as an uninterruptibleelectricity supply, servo motor, air-conditioner …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 1, 2020 · pp. 15–36 Read article
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Quantum Behavior of Charge Carriers in a Symmetrical Double Gate MOSFET
Abstract: Our earlier work on modeling of single gate n-channel metal oxide semiconductor field effect transistor (MOSFET) has been extended to discuss the quantum behavior of charge carriers in symmetrical double gate (DG) MOSFET. The potential profile in the channel region of DG MOSFET has been obtained in parabolic approximation. The parabolic potential facilitates analytical expression for electric field. The appropriate Schrodinger’s equation has been solved to obtain wave functions in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 1, 2021 · pp. 17–28 Read article
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Review on Design and Plan for Installation of Solar PV Modules on University Building
Abstract: AbstractThe power generation sector is capable of generating around 152 Giga Watt but still 17 per cent villages of India generally termed as deserted or mobile areas are still non - electrified in figures it is around 450 million people who lived without electricity till the year 2008. The power sector uses the coal as a primary source of fuel. A report on behalf of ministry of coal said that …
Published in Recent Trends in Fluid Mechanics · Vol. 6, Issue 3, 2019 · pp. 12–16 Read article
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Self-Compensation of Commutation Phase Error for Brushless DC Motor
Abstract: BLDC motors are synchronous motors powered by DC electricity via an inverter which produces an AC electric current to drive each phase of the motor via a closed loop controller. Electronic commutation is the on-and-off of the semiconductor switches at appropriate time to turn stator windings. Commutation phase ripple is generated due to the different exchange rate between outgoing phase current and incoming phase current of inverter during commutation period. …
Published in Trends in Electrical Engineering · Vol. 8, Issue 3, 2018 · pp. 72–81 Read article