All articles
42 articles
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Non-Lethal Protection of Farmlands Against Wild Animals and Crop Estimation
Abstract: This paper is an integrated smart system that aims to enhance productivity related to agriculture along with agricultural safety through modern technology. Crop estimation system uses IoT sensors and machine learning algorithms for the analysis of real-time environmental data in terms of soil moisture, temperature, pH levels, and humidity. This data will further be used to provide the optimal crop for cultivation and appropriate fertilizer requirements for prediction of requirements. …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 18–24 Read article
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Implementation of STATIC-RANDOM-ACCESS-MEMORY-Based In-Memory Computing-architecture for improving Energy Efficiency
Abstract: The in-memory-computing architecture the improvement of big data and high-performance computing. In memory-computing (IMC) as reduces the latency and power consumption of data processing. Proposed research paper static random-access memory-based IMC architecture. By completing internal write-back, NMOS transistors increase computational efficiency and eliminate the need to read the computational output right away. A 128×128 STATIC-RANDOM-ACCESS-MEMORY-IMC macro chip is designed using the 78-nm technology. The energy efficiency of 55.3TOPS/W with supply …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 25–35 Read article
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Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element
Abstract: Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge frequencies. To lower its latency, the C-element has additionally …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 36–44 Read article
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RTL to GDSII Implementation UART using Verilog and Cadence tools
Abstract: The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 1–7 Read article
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Thevenin Impedance Networks for Spice Simulation Using Analog Behavioural Modelling
Abstract: PSPICE/OrCAD software analog behavioral modeling (FREQ) option is used to obtain equivalent circuits for Thevenin equivalent resistance to be used for three types of applications for different circuits (other different networks with these Thevenin models at DC), and Spice files are described to simulation circuits with AC analyses. Three different applications are useful in linear integrated circuits using DC Thevenin resistance of two networks are considered. Firstly, the DC Thevenin …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 39–46 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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Design and Implementation of Low Latency 16-bit Full Adder
Abstract: In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing and systems play a vital role in the analysis and computation of data representation. Electronic systems have gradually become faster and smaller scale. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 21–31 Read article
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Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips
Abstract: At lower nodes of complementary metal-oxide semiconductor (CMOS) technology, noise within a chip increase due to a drastic increment in interconnects within a given area. To improve the noise immunity of a chip, a Schmitt trigger circuit is used as a buffer instead of a simple CMOS inverter at various intervals along the metal interconnect. The use of a Schmitt trigger circuit not only makes the chip noise immune but …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 11–20 Read article
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RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools
Abstract: Exploring the RTL-to-GDS implementation of a high-speed on-chip 32:1 serializer, this study investigates the integration of open-source tools within VLSI design, emphasizing sustainable practices in the semiconductor industry while operating at the nanometer scale. Addressing methodologies for optimizing power consumption and chip area utilization, particularly focusing on efficient use of non-renewable resources. The study is set against the backdrop of advanced 7nm FinFET technology, critical for enabling efficient data transmission …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 1–10 Read article
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Vehicle Black Box Systems: Evolution, Implementation, and Impact on Road Safety
Abstract: The main goal is to create a Black Box System for Vehicle that can be used to enhance road safety. To record accident data, as well as the location of the accident, an SOS message, the temperature of the car, and an automatically administered breathalyzer test for the driver, we are developing a black box in this project. The Black Box for Vehicle can aid in making automobiles safer, gather …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 38–46 Read article
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Surveillance Car using ESP32 Cam Module by using GAN Model
Abstract: This paper shows the Surveillance Car system which leverages the ESP32 Cam module and incorporates advanced image processing through a Generative Adversarial Network (GAN) model to redefine the landscape of mobile surveillance systems. The ESP32 Cam serves as the core hardware platform, offering compact design and wireless capabilities for real-time image capture and remote monitoring. The system’s innovation lies in the integration of a GAN model for image processing, enhancing …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 28–37 Read article
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Performance and Reliability Analysis of NAND Flash Memory through Characterization
Abstract: An extensive review of NAND flash memory technology is given in this study, with an emphasis on its design, guiding principles, and most recent developments. The importance of NAND flash memory in contemporary digital storage systems is discussed in general terms, emphasizing how widely used it is in everything from consumer electronics to business storage solutions. The underlying architecture of NAND flash memory, including the arrangement of memory cells, pages, …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 21–27 Read article
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Optimizing Routing and Placement of VLSI Circuits with Differential Algorithms and Neural Networks
Abstract: The performance of modern VLSI systems is heavily influenced by power constraints, necessitating precise power estimation and effective optimization techniques. Traditional methods, such as gate-level simulations, are often slow and computationally intensive. This paper introduces DRPENN (Differential Algorithm for Routing and Placement Optimization using Neural Networks), an innovative solution that combines a Switching Activity Estimator (SAE) with a neural network-assisted differential algorithm. By leveraging toggle rates from simulations to train …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 14–20 Read article
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Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed
Abstract: This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 1–13 Read article
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Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Abstract: The three operands binary adder is a basic function used in the creation of modular arithmetic in various algorithms, such as the pseudorandom bit generator and cryptography. The CS3A carry save adder is commonly used to perform this operation. Nevertheless, the operation's outcome delayed the transmission of O(n) because of the ripple carry step. A dual-optoic adder for parallel prefix computation, such as the Han-Carlson method, can be used to …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 14–22 Read article
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High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Abstract: This paper focuses on the design and optimization of latch comparators for high-speed data converter applications. The performance of different comparator architectures is compared in terms of speed, power consumption, and noise performance. The proposed latch comparator architecture uses a preamplifier to boost gain and sensitivity, and a latch to store the output signal. The latch comparator design is optimized for low power consumption and high speed, and is implemented …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 23–32 Read article
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Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article
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Exploring the Dynamics of Memristors: Mechanisms, Models, and Multifaceted Applications
Abstract: Memristors, a fundamental electronic component first proposed by Leon Chua in 1971, have garnered significant attention due to their unique electrical behavior and promising applications in various fields. This paper provides a comprehensive overview of memristors, covering their basic principles, characteristics, fabrication methods, and applications of Memristor and it’s significance with flux charge linkage. The paper also shows study of a grounded memristor emulator and it’s working as a memristor …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 1–7 Read article
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Hardware Synchronization for Embedded Multi-core Processors
Abstract: The focus is not on whether multi-core systems are becoming prevalent, but on how microcontroller architectures should be designed to comply with stringent field requirements. This paper illustrates the transition from single to multiple cores, ensuring coherence and consistency in shared memory through hardware mechanisms. Hardware barriers are implemented to allow for point-to-point synchronization between processor cores. Practical experiments center on the initial stages of transforming single-core systems into dual-core …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 33–42 Read article
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Design and Simulation of Forging Die Towards Improving Life of Closed Die
Abstract: Forging is the metal forming process which is used for forming complex shaped component with geometrical accuracy. More than fifty percent of the forgings are processed through this way. Forged components required in many engineering sectors, most of them in the automotive sector. The majority of the safety critical component and load bearing structural components are process through it. By using forging process production of complex component is faster with …
Published in Journal of VLSI Design Tools and Technology Read article